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target specification ade3700 analog lcd display engine for xga and sxga resolutions ? this is preliminary information on a new product forseen to be developed. details are subject to change without notice. october 2003 1/89 feature overview n programmable context sensitive? scaling n high-quality up-scaling and down-scaling n integrated 9-bit adc/pll n iqsync? autosetup n integrated programmable timing controller n integrated pattern generator n perfect picture? technology n srgb 3d color warp n integrated osd n advanced emi reduction features n framelock operation with safety mode? n serial i2c interface n low power 0.18 m process technology general description ade3700 devices are a family of highly-integrated display engine ics, enabling the most advanced, flexible, and cost-effective system-on-chip solutions for analog-only input lcd display applications. the ade3700 covers the full range of xga and sxga analog-only applications including smart panel designs. the ade3700 family is pin-to-pin compatible and comes in a low-cost, 128-pin lqfp package. ade3700 devices use the same software platform and are backward-compatible with the previous generation of ade3xxx scaling engines. lcd scaler product selector product package output format support input interface support resolution tcon analog dvi yuv ade3700x 128 lqfp up to xga 75 hz yes ade3700xt 128 lqfp up to xga 75 hz yes yes ADE3700SX 128 lqfp up to sxga 75 hz yes line-lock pll fast and accurate ? phase ? position ?level ? clock srgb 3d color warp temporal & spatial dithering interlace analog video 30-bit programmable gamma table lcd panel microcontroller firmware rom on-screen display engine pattern generator programmable timing controller (tcon) rsds lvcmos emi reduction ? per pin delay ? slew rate control ? spread spectrum ? data inversion ade 3700 i2c adjustments of: iq scaling ? rgb signals triple 9-bit adc to tft programmable output formatter engine with context sensitive ? filtering mode detection
ade3700 2/89 third generation context sensitive? scaler l sharper text with edge enhancement l ram based coefficients for unique customization l 5:1 upscale and 2:1 downscale l independent x - y axis zoom and shrink analog rgb input l 140 mhz 9-bit adc l ultra low jitter digital line lock pll l composite sync and sync on green support iqsync? autosetup l autosetup configures phase, clock, level, and position l supports continuous calibration for reduced user intervention l automatically detects activity on input l compatible with all standard vesa and gtf modes perfect picture? technology l programmable 3d color warp l digital brightness, contrast, hue, and saturation gamma controls for all inputs l simple white point control l compatible with srgb standard l video & picture windowing l supports up to 7 different windows l independent window controls for contrast brightness, saturation, hue and gamma perfect color? technology l true color dithering for 12- and 18-bit panels l temporal and spatial dithering l 30-bit programmable gamma table osd engine l 256 ram based 12x18 characters l 1- and 4-bit per pixel color characters l bordering, shadowing, transparency, fade-in, and fade-out effects l supports font rotation l up to 4 sub windows l 32-entry truecolor lut programmable timing controller (tcon) l highly programmable support for xga smartpanels l dual-function lvcmos and rsds outputs l supports 18-, 24-, 36-, and 48-bit rsds outputs l advanced flicker detection and reduction l 12 programmable timing signals for row/ column control l wide range of drivers & tcon compatibility l simulation tools for easy programming l supports complex polarity generation for ips panels advanced emi reduction features l flexible data inversion / transition minimization, single, dual, and separate l per pin delay, 0 to 6ns in 0.4ns increments l adaptive slew rate control outputs l differential clock l spread spectrum -programmable digital fm modulation of the output clock with no external components output format l supports resolutions up to sxga @ 75hz l supports 6- or 8-bit panels l supports double or single pixel wide formats
3/89 ade3700 table of contents chapter 1 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 pin descriptions .......................................................................................................... ........ 7 chapter 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.1 global control ..... ............................................................................................................... 11 2.2 fm frequency synthesizer ................................................................................................ 16 2.3 analog-to-digital converter (adc) ..................................................................................... 17 2.4 line lock pll .............................................................................................................. ...... 18 2.5 sync retiming (srt) ........................................................................................................ .23 2.6 sync measurement ........................................................................................................... .25 2.7 sync multiplexer (smux) ................................................................................................... 3 2 2.7.1 functional description ................................................................................................... ....................33 2.7.2 example .................................................................................................................. ...........................34 2.8 data multiplexer ........................................................................................................... ...... 37 2.9 data measurement (dmeas) ............................................................................................ 38 2.9.1 edge intensity ........................................................................................................... .........................38 2.9.2 pixel sum ................................................................................................................ ...........................38 2.9.3 minimum/maximum pixel .................................................................................................... ...............38 2.9.4 pixel cumulative distribution (pcd) ...................................................................................... ............39 2.9.5 horizontal position ...................................................................................................... .......................39 2.9.6 vertical position ........................................................................................................ .........................39 2.9.7 de size .................................................................................................................. ............................40 2.10 lcd scaler ................................................................................................................ ......... 42 2.11 output sequencer .......................................................................................................... .... 45 2.11.1 frame synchronization ................................................................................................... ...................45 2.11.2 timing unit ............................................................................................................. ............................45 2.11.3 signal generation ....................................................................................................... .......................45 2.12 timing controller (tcon) ..... ............................................................................................. 48 2.13 pattern generator ......................................................................................................... ..... 54 2.13.1 screen split ............................................................................................................ ...........................54 2.13.2 pattern engine .......................................................................................................... .........................55 2.13.3 borders ................................................................................................................. .............................55 2.14 srgb ...................................................................................................................... ............ 60 2.14.1 parametric gamma, digital contrast / brightness on multiple windows ...........................................60 2.14.2 color space warp ........................................................................................................ ......................60 2.15 on-screen display (osd) .................................................................................................. 6 2 2.15.1 osd access via i2c ...................................................................................................... ....................62 2.16 flicker ................................................................................................................... .............. 68
ade3700 4/89 2.17 gamma ..................................................................................................................... ..........70 2.18 apc ....................................................................................................................... .............71 2.19 output multiplexer ..... .........................................................................................................72 2.19.1 sub block function ...................................................................................................... ..................... 73 2.19.2 rsds .................................................................................................................... ............................ 76 2.19.3 per pin delay ........................................................................................................... ......................... 77 2.20 pulse width modulation (pwm) ..........................................................................................80 2.21 dft block ................................................................................................................. ..........81 2.22 i2c ram addresses ...........................................................................................................8 3 chapter 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.1 absolute maximum ratings ................................................................................................84 3.2 power consumption matrices .............................................................................................84 3.3 nominal operating conditions ............................................................................................85 3.4 preliminary thermal data ..... ..............................................................................................85 3.5 preliminary dc specifications .. ..........................................................................................85 3.5.1 lvttl 5 volt tolerant inputs with hysteresis ............................................................................. ...... 85 3.5.2 lvttl 5 volt tolerant inputs ............................................................................................. ................ 85 3.5.3 lvttl 5 volt tolerant i/o with hysteresis ................................................................................ ........ 86 3.5.4 lvttl outputs ............................................................................................................ ...................... 86 3.6 preliminary ac specifications . ..........................................................................................86 chapter 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 chapter 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5/89 ade3700 1 general information the ade3700 family of devices is capable of implementing all of the advanced features of today's lcd monitor products. for maximum flexibility, an external microcontroller ( mcu) is used for controlling the ade3700 and other monitor functions. the ade3700 architecture unburdens the mcu from all data -intensive pixel manipulations, providing an optimal blend of features and code customizing without incurring the cost of a 16-bit processor or memory. the key interactions between the monitor mcu and the ade3700 can be broken down into the features shown in the table below. figure 1: ade3700 block diagram table 1: ade3700 features (sheet 1 of 2) feature description of ade3700 operation blocks used pages power-up / initialize when power is first applied, the ade3700 is asynchronously reset from a pin. the mcu typically programs the ade3700 with a number of default values and sets up the ade3700 to identify activity on any of the input pins. all pre- configured values and rams, such as dvi settings, line-lock pll settings, osd characters, lcd timing values (output sequencer), scale kernels, gamma curves, srgb color warp, apc dithering, output pin configuration (omux), etc. can be pre-loaded into the ade3700. the typical end state is that the ade3700 is initialized into a low power mode, ready to turn active once the power button is pressed. glbl smeas llk adc osd scaler gamma srgb outseq tcon apc omux 11 25 18 17 62 42 70 60 45 48 71 72 activity detect when the monitor has been powered on, the inputs can be monitored for active video sources. based on the activity monitors, the mcu chooses an input or power down state. smeas 25 lcd timing controller fm freq. synthesizer llkpll inclk sclk dotclk color management osd gamma lut data ctrl analog dmeas smeas output format pattern generator sclk frequency synthesizer scaler port
ade3700 6/89 sync / timing measurement once an input source is selected, all available information on frequencies and line/pixel counts is measured for the selected source and made available to the mcu. smeas 25 mode set once the mcu has determined the matching video mode or calculated a video mode using a gtf algorithm, the datapath is programmed to drive the flat panel. clock frequencies for the internal memory and datapath are also set at this time. glbl llk srt dmux smux scaler 11 18 23 37 32 42 autotune when the mcu calls for an autotune, the mcu sets up an iterative loop to search for the best phase, gain, offset, etc. at each step of the loop, the mcu kicks off a test in which the ade3700 which performs extensive statistical analysis of the incoming data stream. the results of the analysis are made available to the mcu which is responsible for the optimization algorithm. dmeas llk adc smux srt 47 18 17 32 23 digital contrast / brightness in response to user osd control, the mcu can program single 8-bit registers that set brightness and contrast for each color channel independently. srgb 60 white point control in response to user osd control, the mcu can program three 8-bit registers that set the white point for the output. srgb 60 gamma adjustment the mcu can program the gamma rams to implement 10-bit accurate color transformations. gamma 70 srgb control the srgb block allows simple, intuitive color control with just a few registers. srgb 60 pattern generation for production testing, the ade3700 can be programmed by the mcu to output a wide set of test patterns. pgen 54 flicker reduction for smart panel applications, the mcu can set up the flicker detection block to report any correlation with the polarity inversion signal. the mcu can then change the polarity inversion to a non-correlating pattern to eliminate flicker. flicker tcon 68 48 backlight control the ade3700 provides two pwm outputs for direct control of the power components in a typical backlight. the mcu sets up the registers and enables the function. pwm 80 low power state to enter a low power state, the mcu can gate of most of the clocks and put the analog blocks into a low power standby state. glbl 11 table 1: ade3700 features (sheet 2 of 2) feature description of ade3700 operation blocks used pages
7/89 ade3700 pin descriptions 1.1 pin descriptions table 2: pinout (sheet 1 of 4) lqfp128 name type description 32 xvdd18 power crystal oscillator 1.8v vdd 31 xtal_out output crystal oscillator output 30 xtal_in input crystal osc illator input 29 xgnd power crystal oscillator ground 19 xclk_en input crystal clock output enable 18 xclk output crystal clock buffered output 34 vsync input vertical sync input 21 tstclk input connect to digital ground 65 tst_scan input connect to digital ground 8 tcon7 output tcon output 7 9 tcon6/ovs output tcon output 6/output vertical sync 10 tcon5/ohs output tcon output 5/output horizontal sync 11 tcon4/ode output tcon output 4/output data enable 12 tcon3 input/output tcon output 3 13 tcon2 input/output tcon output 2 14 tcon1 input/output tcon output 1 15 tcon0 input/output tcon output 0 17 sda open drain i/o i2c data 16 scl input i2c clock 20 resetn input reset input, active low 54 refr passive 1% 15.0 kohm resistor to analog ground 55 refmr passive connect to analog ground 48 refmg passive connect to analog ground 41 refmb passive connect to analog ground 47 refg passive 1% 15.0 kohm resistor to analog ground 58 refcr passive 100nf capacitor to analog ground 51 refcg passive 100nf capacitor to analog ground 44 refcb passive 100nf capacitor to analog ground 40 refb passive 1% 15.0 kohm resistor to analog ground 26 pvdd18 power pll 1.8v vdd 28 pvdd18 power pll 1.8v vdd 25 pgnd power pll ground 27 pgnd power pll ground 105 avs output alternate vertical sync 126 orb7 input/output output port b: red data 7 127 orb6 input/output output port b: red data 6
pin descriptions ade3700 8/89 128 orb5 input/output output port b: red data 5 1 orb4 input/output output port b: red data 4 2 orb3 input/output output port b: red data 3 3 orb2 input/output output port b: red data 2 4 orb1 input/output output port b: red data 1 5 orb0 input/output output port b: red data 0 86 ora7 output output port a: red data 7 87 ora6 output output port a: red data 6 88 ora5 output output port a: red data 5 89 ora4 output output port a: red data 4 90 ora3 output output port a: red data 3 95 ora2 output output port a: red data 2 96 ora1 output output port a: red data 1 97 ora0 output output port a: red data 0 103 ahs output alternate horizontal sync 112 ogb7 input/output output port b: green data 7 113 ogb6 input/output output port b: green data 6 114 ogb5 input/output output port b: green data 5 115 ogb4 input/output output port b: green data 4 120 ogb3 input/output output port b: green data 3 121 ogb2 input/output output port b: green data 2 122 ogb1 input/output output port b: green data 1 123 ogb0 input/output output port b: green data 0 74 oga7 output output port a: green data 7 75 oga6 output output port a: green data 6 76 oga5 output output port a: green data 5 77 oga4 output output port a: green data 4 78 oga3 output output port a: green data 3 79 oga2 output output port a: green data 2 82 oga1 output output port a: green data 1 83 oga0 output output port a: green data 0 102 ade output alternate data enable 104 oclk output output clock 98 obb7 input/output output port b: blue data 7 99 obb6 input/output output port b: blue data 6 100 obb5 input/output output port b: blue data 5 101 obb4 input/output output port b: blue data 4 table 2: pinout (sheet 2 of 4) lqfp128 name type description
9/89 ade3700 pin descriptions 108 obb3 input/output output port b: blue data 3 109 obb2 input/output output port b: blue data 2 110 obb1 input/output output port b: blue data 1 111 obb0 input/output output port b: blue data 0 66 oba7 output output port a: blue data 7 67 oba6 output output port a: blue data 6 68 oba5 output output port a: blue data 5 69 oba4 output output port a: blue data 4 70 oba3 output output port a: blue data 3 71 oba2 output output port a: blue data 2 72 oba1 output output port a: blue data 1 73 oba0 output output port a: blue data 0 56 inr input analog video port: red channel input 49 ing input analog video port: green channel input 42 inb input analog video port: blue channel input 35 hsync input horizontal (or composite) sync input 7 dvdd33 power digital 3.3v vdd 64 dvdd33 power digital 3.3v vdd 80 dvdd33 power digital 3.3v vdd 91 dvdd33 power digital 3.3v vdd 106 dvdd33 power digital 3.3v vdd 119 dvdd33 power digital 3.3v vdd 23 dvdd18 power digital 1.8v vdd 62 dvdd18 power digital 1.8v vdd 84 dvdd18 power digital 1.8v vdd 93 dvdd18 power digital 1.8v vdd 117 dvdd18 power digital 1.8v vdd 124 dvdd18 power digital 1.8v vdd 6 dgnd power digital ground 22 dgnd power digital ground 24 dgnd power digital ground 63 dgnd power digital ground 81 dgnd power digital ground 85 dgnd power digital ground 92 dgnd power digital ground 94 dgnd power digital ground 107 dgnd power digital ground table 2: pinout (sheet 3 of 4) lqfp128 name type description
pin descriptions ade3700 10/89 116 dgnd power digital ground 118 dgnd power digital ground 125 dgnd power digital ground 33 csync input composite sync input - for sync on green 36 avdd33 power analog 3.3v vdd 43 avdd33 power analog 3.3v vdd 50 avdd33 power analog 3.3v vdd 57 avdd33 power analog 3.3v vdd 46 avdd18 power analog 1.8v vdd 53 avdd18 power analog 1.8v vdd 60 avdd18 power analog 1.8v vdd 37 agnd power analog ground 39 agnd power analog ground 45 agnd power analog ground 52 agnd power analog ground 59 agnd power analog ground 61 agnd power analog ground 38 advdd18 power 1.8v vdd table 2: pinout (sheet 4 of 4) lqfp128 name type description
11/89 ade3700 global control 2 functional description 2.1 global control the global control block is responsible for: l selecting clock sources l power control l i2c control l sclk frequency synthesizer control l block by block synchronous reset generation the global control block runs on the xclk clock domain which is required to be active for programming. the clock domains of all other blo cks are set in the global control block. for i2c access, the requested block must be driven with a valid clock frequency greater than 10 mhz. clock domains are shown in figure 2 . to program the sclk frequency synthesizer to a desired frequency (f out , in mhz), the f ollowing equations apply. figure 2: global control block diagram table 3: sclk frequency synthesizer programmable values (sheet 1 of 2) frequency range sdiv f out < 8 x f xclk and f out 3 4 x f xclk 0 f out < 4 x f xclk and f out 3 2 x f xclk 1 ade3700 i2c pwm sync measure global sync re-time adc (analog) adc digital i/f line lock pll data measure lcd scaler pattern generator srgb gamma osd apc output multiplexer flicker detection output sequencer tcon sclk freq. synthesizer fm freq. synthesizer xclk domain inclk domain sclk domain dotclk domain data mcu (scl, sda) pc analog inr, g, b v, h, csync ora oga oba orb ogb obb oclk ode ohs ovs tcon
global control ade3700 12/89 md = int(f xclk x (2 (6 + ndiv - sdiv) ) / f out ) pe = int((2 15 ) x (md + 1 - f xclk x (2 (6 + ndiv - sdiv) ) / f out )) where f xclk is the external crystal frequency in mhz (typically 27). the maximum sclk frequency generated by this block is f xtal x 2 (2+ndiv) . for the lowest power operation, all clock sources should be set to the zero setting and the analog power disables should be set. in this condition, only the crystal clock domain (xclk) is running and blocks in inclk or dotclk domains may not be accessible through the i2c interface. the following modules can have their clocks disabled to reduce power consumption when the chip is in steady-state mode: flk, osd, pgen, dft, and dmeas. also, the clock to the tcon can be disabled for non-smart panel applications. note that the osd module has a special power bypass bit that must be enabled when the osd clock is disabled. also, the clock to all i2c registers associated with modules in the inclk and dotclk domains can be disabled after the chip is configured to reduce power in steady-state mode. note that during chip configuration, all i2c clocks must be enabled. an asynchronous clock enable override signal must be disabled to allow control of individual module clock signals. f out < 2 x f xclk and f out 3 f xclk 2 f out < f xclk and f out 3 f xclk / 2 3 f out < f xclk /2 and f out 3 f xclk / 4 4 f out < f xclk /4 and f out 3 f xclk / 8 5 f out < f xclk /8 and f out 3 f xclk / 16 6 f out < f xclk /16 and f out 3 f xclk / 32 7 table 3: sclk frequency synthesizer programmable values (sheet 2 of 2) frequency range sdiv
13/89 ade3700 global control table 4: global registers (sheet 1 of 4) register name addr. mode bits default description glbl_null_addr 0x0000 read [7:0] chip revision id glbl_clk_src_sel_0 0x0001 [7] 0x0 reserved r/w [6:4] 0x5 dotclk source 0x0: testclk pin 0x1: sclk freq synth 0x2: fm freq synth (normal) 0x3: inclk source 0x4: clkin pin 0x5: crystal clock 0x6: 0 0x7: reserved r/w [3:0] 0xa inclk source 0x0: testclk pin 0x1: nc 0x2: adc clock red 0x3: adc clock green 0x4: adc clock blue 0x5: sclk freq synth 0x6: nc 0x7: llk pll (adc input) 0x8: clkin pin 0x9: fm freq synth 0xa: crystal clock 0xb: 0 0xc - 0xf: reserved glbl_clk_src_sel_2 0x0002 [7] 0x0 reserved r/w [6:4] 0x4 llk ctrl clk source 0x0: testclk pin 0x1: sclk freq synth 0x2: llkpll control clock (normal) 0x3: clkin pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: reserved [3] reserved r/w [2:0] 0x4 llk zero clk source 0x0: testclk pin 0x1: sclk freq synth 0x2: llkpll zero clock (normal) 0x3: clkin pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: reserved
global control ade3700 14/89 glbl_clk_inv 0x0003 [7:5] 0x0 reserved r/w [4] 0x0 invert llpll control clock r/w [3] 0x0 invert llpll zero clock r/w [2] 0x0 invert adc sample clock r/w [1] 0x0 invert dot clock r/w [0] 0x0 invert input clock glbl_clk_enable_0 0x0004 [7:1] 0x0 reserved r/w [0] 0x1 clock enable async override glbl_ana_pwr 0x0005 [7:5] 0x0 reserved r/w [4] 0x1 blue adc power down r/w [3] 0x1 green adc power down r/w [2] 0x1 red adc power down [1:0] 0x0 reserved glbl_xk_srst 0x0006 [7:3] 0x0 reserved r/w [2] 0x0 smeas block reset, synchronous to xclk r/w [1] 0x0 srt block reset, synchronous to xclk r/w [0] 0x0 frame sync block reset, synchronous to xclk glbl_i2c_ctrl 0x0007 [7:3] 0x0 reserved r/w [2] 0x0 disable i2c auto increment r/w [1] 0x0 sda pmos enable r/w [0] 0x0 bypass i2c filter glbl_xtal_ctrl 0x0008 [7:1] 0x0 reserved r/w [0] 0x1 crystal oscillator enable glbl_sclk_synth_ctrl 0x0009 [7:5] 0x0 reserved r/w [4:3] 0x0 xtal frequency multiplier ndiv 0x0: f xclk = 54mhz 0x1: f xclk = 27mhz (normal) 0x2: f xclk = 13.5mhz 0x3: reserved r/w [2] 0x0 sclk frequency synthesizer ext_pll (normal operation = 0) r/w [1] 0x0 sclk frequency synthesizer pll_sel (normal operation = 1) r/w [0] 0x1 sclk freq synth control disable (normal operation = 0) table 4: global registers (sheet 2 of 4) register name addr. mode bits default description
15/89 ade3700 global control glbl_sclk_md_sd 0x000a r/w [7:3] 0x0 sclk frequency synthesizer md, range is [16,31] r/w [2:0] 0x0 sclk frequency synthesizer sdiv, range is [0,7] glbl_sclk_pe_l 0x000b r/w [7:0] 0x0 sclk frequency synthesizer pe, range is [0, 32767] glbl_sclk_pe_h 0x000c r/w [7:0] glbl_tst_ctrl 0x000d [7:1] 0x0 reserved r/w [0] 0x0 functional test mode enable glbl_comp_pad_ctrl 0x000e [7:2] 0x0 reserved r/w [1] 0x0 compensation pad tq (test mode) r/w [0] 0x1 compensation pad en (enable) glbl_sclk_ctrl 0x0010 [7:5] 0x0 reserved r/w [4] 0x0 invert sclk [3] 0x0 reserved r/w [2:0] 0x0 sclk source select 0x0: testclk pin 0x1: sclk freq synth 0x2: fm freq synth (normal) 0x3: inclk source 0x4: clkin pin 0x5: crystal clock 0x6: 0 0x7: reserved glbl_bpad_en 0x0011 r/w [3:0] 0x0 for each bit n (0 to 3) in the ls nibble, 0: tcon[n] pin is tcon output 1: tcon[n] pin is input for testing r/w [4] 0x0 port b input mode enable (production test only) glbl_ik_srst 0x0020 r/w [7] 0x0 reserved r/w [6] 0x0 dft block reset synchronous to inclk r/w [5] 0x0 adc block reset synchronous to inclk r/w [4] 0x0 scaler block reset synchronous to inclk r/w [3] 0x0 reserved r/w [2] 0x0 reserved r/w [1] 0x0 dmeas block reset synchronous to inclk r/w [0] 0x0 smux block reset synchronous to inclk glbl_shadow_en 0x0021 [7:1] 0x0 reserved r/w [0] 0x0 shadow registers sync on frame boundary table 4: global registers (sheet 3 of 4) register name addr. mode bits default description
fm frequency synthesizer ade3700 16/89 2.2 fm frequency synthesizer the fm frequency synthesizer can create a clock up to eight times the crystal input clock using a digital frequency synthesizer. the modulation period and amplitude are directly controlled by i2c registers. the i2c interface runs in the llk_ctrl clock domain, which must be active for access. the relationship of the output frequency (f out ) to the 32-bit phase_rate value and the crystal frequency (f xclk ) is: f out = f xclk * 2 27+ndiv / phase_rate where f out and f xclk are in mhz. the maximum output frequency of the fm frequency synthesizer is f xtal x 2 (2+ndiv) . note that native duty cycle of the fm frequency synthesizer is not 50/50, so it is recommended to either enable the divide-by-two in the fm synthesizer block for frequencies up to f xclk x 2 (1+ndiv) (typically 108 mhz) or set the output mux to a double wide output mode for pixel clocks above f xclk x2 (1+ndiv) . this will ensure a 50% duty clock on the output. glbl_inclk_gate_ctrl 0x0022 [7:3] 0x0 reserved r/w [2] 0x1 enable dft clock r/w [1] 0x1 enable dmeas clock r/w [0] 0x1 enable inclk to i2c registers glbl_dk_srst 0x0040 [7] 0x0 reserved r/w [6] 0x0 pgen block reset synchronous to dotclk r/w [5] 0x0 omux block reset synchronous to dotclk r/w [4] 0x0 apc block reset synchronous to dotclk r/w [3] 0x0 osd block reset synchronous to dotclk r/w [2] 0x0 gamma block reset synchronous to dotclk r/w [1] 0x0 osq block reset synchronous to dotclk r/w [0] 0x0 scale block reset synchronous to dotclk glbl_osd_power_ctrl 0x0041 [7:1] 0x0 reserved r/w [0] 0x0 osd bypass (when clock disabled) glbl_dotclk_gate_ctrl 0x0042 [7:5] 0x0 reserved r/w [4] 0x1 enable flk clock r/w [3] 0x1 enable tcon clock r/w [2] 0x1 enable osd clock r/w [1] 0x1 enable pgen clock r/w [0] 0x1 enable dotclk to i2c registers table 4: global registers (sheet 4 of 4) register name addr. mode bits default description
17/89 ade3700 analog-to-digital converter (adc) 2.3 analog-to-digital converter (adc) the analog port consists of three 9-bit rgb adcs with preamp, gain/offset adjustment and d igital filtering. the i2c interface for the adc block is in the inclk clock domain which must be active for programming. the relationship of input voltage, gain and offset register settings to output code is approximately as follows: output_code_8b = 457 x offset / 2 8 + 181 x gain x input_mv / 2 16 - 125 x gain x offset / 2 16 - 219 table 5: fm frequency synthesizer registers register name addr mode bits default description fm_fs_ctrl 0x0830 [7:4] reserved r/w [3] 0x0 clear the fm synthesizer r/w [2] 0x0 clear the fs accumulator r/w [1] 0x0 activate the frequency modulation r/w [0] 0x0 divide the output by 2 fm_fs_pr_0 0x0831 r/w [7:0] 8000000 phase rate fm_fs_pr_1 0x0832 r/w [7:0] fm_fs_pr_2 0x0833 r/w [7:0] fm_fs_pr_3 0x0834 r/w [7:0] fm_fs_amplitude 0x0835 r/w [7:0] 0x0 lsb = 72 ps fm_fs_periodx64 0x0836 r/w [7:0] 0x80 lsb = 1.185 us fm_fs_pulse_ext 0x0837 r/w [7] 0x0 enable [6:3] reserved r/w [2:0] 0x0 value table 6: adc registers (sheet 1 of 2) register addr. mode bits default description adc_dither 0x0324 [7] reserved r/w [6] 0x0 dither horizontally r/w [5] 0x0 dither vertically r/w [4] 0x0 dither temporally r/w [3] 0x0 force dither high r/w [2] 0x0 enable dither [1:0] 0x0 reserved adc_offset_r 0x0326 r/w [7:0] 0x0 offset control, red channel adc_offset_g 0x0328 r/w [7:0] 0x0 offset control, green channel
line lock pll ade3700 18/89 2.4 line lock pll the line lock pll recovers a sample clock from an incoming hsync source. the response characteristics of the line lock pll can be adjusted for optimum response time and jitter filtering. the phase of the sample clock can be digitally adjusted in steps of 289 ps (with a 27-mhz crystal). the i2c interface of the line lock pll is in the llk_ ctrl clock domain which must be active for programming. the pll filter has three ranges with independent filter parameters. when the phase detector error stays below a programmable threshold for a programmable number of input lines, the pll filter coefficients are changed. any phase detector error above the programmed threshold will return the filter to the appropriate level in one line. the operation is shown in figure 3 . the digital loop filter is controlled by three parameters: mfactor, a and b. m_factor is the desired number of clocks per input line. the a and b parameters control the response of the 2nd order digital filter. a and b are composed of a linear and exponential component designated by the l and e suffix, respectively. the relationship of these numbers to the classic 2nd order damping and natural frequency are as follows: damping = al x 2 (ae-12) x sqrt(5 x m_factor / (bl x 2 be )) natural frequency = sqrt(m_factor x 5 x bl x 2 (be-34) ) adc_offset_b 0x0329 r/w [7:0] 0x0 offset control, blue channel adc_gain_r 0x032a r/w [7:0] 0x0 gain control, red channel adc_gain_g 0x032b r/w [7:0] 0x0 gain control, green channel adc_gain_b 0x032c r/w [7:0] 0x0 gain control, blue channel figure 3: line lock pll table 6: adc registers (sheet 2 of 2) register addr. mode bits default description fast slow lock error > slow_tol error <= slow_tol for more than lock_line_nb error > lock_tol more than slow_line_nb of lines error <= lock_tol for of lines
19/89 ade3700 line lock pll table 7: line lock pll registers (sheet 1 of 4) register name addr mode bits default description llk_pll_clear 0x0800 [7:6] reserved r/w [5] 0x0 master reset r/w [4] 0x0 reset the pll synthetic sync r/w [3] 0x0 reset pll offset r/w [2] 0x0 reset pll accumulator r/w [1] 0x0 reset the low pass filter r/w [0] 0x0 reset the pll phase error llk_pll_ctrl 0x0801 r/w [7] reserved r/w [6] 0x0 zero clock delay enable r/w [5] 0x0 0: normal 1: diagnostic mode -- pll uses only fine error r/w [4] 0x0 0: normal 1: diagnostic -- coarse error is multiplied by 2 r/w [3] 0x0 input hsync edge selection 0: rising edge 1: falling edge r/w [2] 0x0 sync on green input selection 0: composite sync (hsync pin) 1: sync on green (csync pin) r/w [1] 0x0 0: normal 1: divide pll clock by 2 r/w [0] 0x0 0: normal 1: free-running mode llk_pll_mfactor_l 0x0802 r/w [7:0] 0x0280 number of clocks in a line llk_pll_mfactor_h 0x0803 r/w [7:0] llk_pll_hperiod_l 0x0804 r/w [7:0] 0x0040 pulse width of synthetic hsync llk_pll_hperiod_h 0x0805 r/w [7:0] llk_pll_phase_rate_init_0 0x0806 r/w [7:0] 0x0 initial phase rate llk_pll_phase_rate_init_1 0x0807 r/w [7:0] fout = fxtal * 2 27+ndiv / phase_rate llk_pll_phase_rate_init_2 0x0808 r/w [7:0] llk_pll_phase_rate_init_3 0x0809 r/w [7:0] llk_pll_phase_rate_init_wr 0x080a r/w [7:1] reserved [0] when written to 1, the pll phase rate is initialized with the initial phase rate register. self clearing.
line lock pll ade3700 20/89 llk_pll_tc_aef 0x080b [7:4] reserved r/w [3:0] 0xa fast time constant a exponent llk_pll_tc_bef 0x080c [7:4] reserved r/w [3:0] 0xa fast time constant b exponent llk_pll_tc_alf 0x080d [7:6] reserved r/w [5:0] 0x20 fast time constant a linear llk_pll_tc_blf 0x080e [7:6] reserved r/w [5:0] 0x20 fast time constant b linear llk_pll_tc_aes 0x080f [7:4] reserved r/w [3:0] 0x6 slow time constant a exponent llk_pll_tc_bes 0x0810 [7:4] reserved r/w [3:0] 0x6 slow time constant b exponent llk_pll_tc_als 0x0811 [7:6] reserved r/w [5:0] 0x20 slow time constant a linear llk_pll_tc_bls 0x0812 [7:6] reserved r/w [5:0] 0x20 slow time constant b linear llk_pll_tc_aek 0x0813 [7:4] reserved r/w [3:0] 0x6 lock time constant a exponent llk_pll_tc_bek 0x0814 [7:4] reserved r/w [3:0] 0x6 lock time constant b exponent llk_pll_tc_alk 0x0815 [7:6] reserved r/w [5:0] 0x20 lock time constant a linear llk_pll_tc_blk 0x0816 [7:6] reserved r/w [5:0] 0x20 lock time constant b linear llk_pll_tc_slow_tol 0x0817 r/w [7:0] 0x80 more than slow_line_nb lines with a phase error less than the slow_tol will set the slow status bit, and the pll will work with the slow time constant. one or more lines with a phase error more than slow_tol will reset the slow status bit, and the pll will work with the fast time constant. lsb of slow tol is approx. 200ps. llk_pll_tc_slow_line_nb 0x0818 r/w [7:0] 0x10 table 7: line lock pll registers (sheet 2 of 4) register name addr mode bits default description
21/89 ade3700 line lock pll llk_pll_lock_tol 0x0819 r/w [7:0] 0x20 more than lock_line_nb lines with a phase error less than the lock_tol will set the lock status bit, and the pll will work with the lock time constant. one or more lines with a phase error more than lock_tol will reset the lock status bit, and the pll will work with the slow time constant. lsb of lock tol is approx. 200ps. llk_pll_lock_line_nb 0x081a r/w [7:0] 0x30 llk_pll_ph_offset 0x081b r/w [7:0] 0x0 phase adjustment. the maximum phase offset value is equal to phase_rate[31:21] or 0x40, whichever is higher. llk_pll_ph_offset_en 0x081c r/w [7] 0x0 phase enable [6] skip pulse [5] skip pulse at every rising edge of hsync [4:0] reserved llk_pll_pulse_high_ext 0x081d r/w [7] 0x0 0: no pulse extend 1: extend pulse (normal) [6:3] reserved r/w [2:0] 0x0 pulse extend amount 0x0: minimum 0x7: maximum (normal) llk_pll_stat_lines_l 0x081e r/w [7:0] 0x10 number of lines to statistically analyze. llk_pll_stat_lines_h 0x081f r/w [7:0] llk_pll_stat_error_inc_lo w 0x0820 [7:0] reserved llk_pll_fine_error_wait 0x0821 [7:4] reserved r/w [3:0] 0x0 wait this number of ctrl_clk cycles before updating the pll. llk_pll_stat_on_vsync 0x0822 [7:2] reserved r/w [1] 0x0 pll statistic synchronize on falling edge of vsync r/w [0] 0x0 pll statistic synchronize on rising edge of vsync llk_pll_mfactor_shadow_l 0x0823 r/w [7:0] 0x80 number of clocks in a line. llk_pll_mfactor_shadow_u 0x0824 r/w [7:0] 0x02 registers 0x0803 and 0x0802 are transferred to those registers according to update_on_venab_fe. table 7: line lock pll registers (sheet 3 of 4) register name addr mode bits default description
line lock pll ade3700 22/89 llk_pll_update 0x0840 r [7] in free-running mode, toggles when status is updated. in one-shot mode, this bit is set when status is ready. [6:2] reserved r/w [1] 0x0 0: free-running mode 1: one-shot mode r/w [0] 0x0 update enable llk_pll_status 0x0841 [7:4] reserved r [3] llk overflow r [2] coarse error = 0 r [1] in slow mode r [0] in lock mode llk_pll_ph_error_l 0x0842 r [7:0] phase error llk_pll_ph_error_h 0x0843 r [7:0] lsb = approx. 200ps llk_pll_phase_rate_0 0x0844 r [7:0] llk phase rate llk_pll_phase_rate_1 0x0845 r [7:0] fout = fxtal * 2 27+ndiv / phase_rate llk_pll_phase_rate_2 0x0846 r [7:0] llk_pll_phase_rate_3 0x0847 r [7:0] llk_pll_phase_rate_i_0 0x0848 r [7:0] integral phase rate llk_pll_phase_rate_i_1 0x0849 r [7:0] llk_pll_phase_rate_i_2 0x084a r [7:0] llk_pll_phase_rate_i_3 0x084b r [7:0] llk_pll_stat_error_mean 0x084c r [7:0] average phase error over stat_lines phase error lsb is approx. 200ps llk_pll_stat_error_pp_l 0x084d r [7:0] peak phase error over stat_lines llk_pll_stat_error_pp_h 0x084e r [7:0] phase error lsb is approx. 200ps llk_pll_stat_error_abs_l 0x084f r [7:0] sum of absolute phase errors over stat_lines phase error lsb is approx. 200ps llk_pll_stat_error_abs_h 0x0850 r [7:0] llk_pll_stat_error_gtx 0x0851 [7:0] reserved table 7: line lock pll registers (sheet 4 of 4) register name addr mode bits default description
23/89 ade3700 sync retiming (srt) 2.5 sync retiming (srt) the sync retiming (srt) block retimes incoming synchronization signals (h sync, v sync, etc) into the xclk and inclk domains. for the xclk domain, the srt has the following functions: l retimes all sync signals going to smeas into the xclk domain. l extracts the vertical sync signal from composite sync signals (ahsync and acsync pins) l divides clocks by 1024 for activity detection purposes. l generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source. l generates a coast signal in the xclk domain for the llpll. table 8: sync retiming registers (sheet 1 of 2) register name addr mode bits default description srtxk_csync_inv 0x01e0 [7:3] 0x0 reserved r/w [2] 0x0 invert filtered vert sync signal r/w [1] 0x0 invert composite sync signal r/w [0] 0x0 invert sog signal srtxk_sog_thr_l 0x01e1 r/w [7:0] 0x080 sog vert sync extractor threshold [7:0] srtxk_sog_thr_h 0x01e2 r/w [7:4] reserved [3:0] sog vert sync extractor threshold [11:8] srtxk_csync_thr_l 0x01e3 r/w [7:0] 0x080 composite sync vertical sync extractor threshold [7:0] srtxk_csync_thr_h 0x01e4 r/w [7:4] reserved [3:0] composite sync vertical sync extractor threshold [11:8] srtxk_vsync_sel 0x01e5 r/w [7:3] reserved [2:0] 0x0 filtered vert sync source select 0x0: avsync pin 0x1: vsync from composite ahsync pin 0x2: vsync from composite acsync pin 0x3: reserved 0x4 - 0x7: reserved srtxk_vsync_thr_l 0x01e6 r/w [7:0] 0x080 filtered vert sync delay [7:0] srtxk_vsync_thr_h 0x01e7 r/w [7:4] reserved r/w [3:0] filtered vert sync delay [11:8]
sync retiming (srt) ade3700 24/89 srtxk_coast_vs_sel 0x01e8 [7:4] 0x0 reserved r/w [3] 0x0 coast signal trigger edge 0: posedge of selected vertical 1: negedge of selected vertical r/w [2:0] 0x0 source select for coast vert sync trigger 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: reserved 0x4: nc 0x5: nc 0x6: srt vsync (filtered vsync) 0x7: reserved srtxk_coast_rise_l 0x01e9 r/w [7:0] 0x0 rising edge of coast, in xclks from vsync trigger srtxk_coast_rise_m 0x01ea r/w [7:0] 0x0 srtxk_coast_rise_h 0x01eb r/w [7:0] 0x0 srtxk_coast_fall_l 0x01ec r/w [7:0] 0x0 falling edge of coast, in xclks from vsync trigger srtxk_coast_fall_m 0x01ed r/w [7:0] 0x0 srtxk_coast_fall_h 0x01ee r/w [7:0] 0x0 srtik_hs_ctrl 0x01f0 [7:3] 0x0 reserved r/w [2] 0x0 resample clock edge to transfer hsync into the inclk domain; depends on llk phase offset value. 0: posedge inclk 1: negedge inclk r/w [1:0] 0x0 horz sync source select for resampling into the inclk domain 0x0: llpll lock sync (normal) 0x1: ahsync pin 0x2: acsync pin 0x3: reserved srtik_vs_sel 0x01f1 [7:2] 0x0 reserved r/w [1:0] 0x0 vert sync source select for resampling 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: srt vsync (filtered vsync) table 8: sync retiming registers (sheet 2 of 2) register name addr mode bits default description
25/89 ade3700 sync measurement 2.6 sync measurement the input sync measurement (smeas) block continuously detects activity from all video sources. the module can measure the characteristics of the sync signals on any input port. the sync measurement module reports the results of the measurements to the system microcontroller. this portion of the sync measurement is fully synchronous on the crystal clock (xclk). another block, the sync retiming block (srt), handles the asynchronous signal transfer of the incoming sync signals. input sync functions: l activity detection l sync management l measurement table 9: sync measurement (sheet 1 of 8) register name addr mode bits default description smeas_act_ctrl 0x0100 [7:4] 0x0 reserved r/w [3] 0x0 enable activity detection in free-running mode. r/w [2] 0x0 freeze results in free-running mode. no meaning in one shot mode. 0: do not freeze the results. new result will be available on the next and subsequent toggle of the polling bit. 1: freeze the current results. the polling bit will still toggle and the block continues to free-run; however, results will not be updated. r/w [1] 0x0 activity detection start. in one-shot mode it triggers the start of a measurement and is reset to zero when the measurement is complete. r/w [0] 0x0 activity detection mode control 0: free-running 1: one shot smeas_act_h_smptm_l 0x0101 r/w [7:0] 0x0 sample time value for clock or hsync activity. in units of xclk_period*256 smeas_act_h_smptm_h 0x0102 r/w [7:0] 0x0 smeas_act_v_smptm_l 0x0103 r/w [7:0] 0x0 sample time value for vsync activity in units of xclk_period*256. jj note: this number must be larger than hsync sample time. smeas_act_v_smptm_h 0x0104 r/w [7:0] 0x0 smeas_act_h_minedge 0x0105 r/w [7:0] 0x0 minimum edge count value for clk or hsync activity. smeas_act_v_minedge 0x0106 r/w [7:0] 0x0 minimum edge count value for vsync activity. smeas_h_tmot_l 0x0107 r/w [7:0] 0x4000 timeout counter value for clk or horizontal measurement in xclks smeas_h_tmot_h 0x0108 r/w [7:0]
sync measurement ade3700 26/89 smeas_v_tmot_l 0x0109 r/w [7:0] 0x1600 timeout counter value for vertical measurement in units of xclk/256 smeas_v_tmot_h 0x010a r/w [7:0] smeas_clear 0x0110 [7:3] reserved r/w [2] 0x0 clear sticky status bits r/w [1] 0x0 clear all out-of-range event counters r/w [0] 0x0 clear all result registers smeas_h_ctrl 0x0111 [7] 0x0 reserved r/w [6] 0x0 enable hsync filter -- all hsync pulses less than smeas_filter_hs_width will be ignored. r/w [5] 0x0 measure hsync in the absence of vsync r/w [4] 0x0 enable horizontal measurement in free- running mode r/w [3] 0x0 horizontal event edge select 0: positive edge 1: negative edge r/w [2] 0x0 freeze horizontal measurements results during free-running mode. no meaning in one shot mode. 0: do not freeze measurement results. new result will be available on the next and subsequent toggle of the polling bit. 1: freeze the current results. the polling bit will still toggle and the block continues to free-running; however, results will not be updated. r/w [1] 0x0 horizontal measurement start in one-shot mode setting this bit triggers the start of a measurement. the bit is reset to zero when the measurement is complete. r/w [0] 0x0 horizontal measurement mode 0: free-running 1: one shot table 9: sync measurement (sheet 2 of 8) register name addr mode bits default description
27/89 ade3700 sync measurement smeas_v_ctrl 0x0112 [7:5] reserved r/w [4] 0x0 enable vertical measurement in free- running mode r/w [3] 0x0 vertical event edge select 0: positive edge 1: negative edge r/w [2] 0x0 freeze vertical measurement results during free-running mode. no meaning in one shot mode. 0: do not freeze the results. new result will be available on the next and subsequent toggle of the polling bit. 1: freeze the current results in free-running mode. the polling bit will still toggle and the block continues to free run; however, results will not be updated. r/w [1] 0x0 vertical measurement start in one-shot mode setting this bit triggers the start of a measurement. the bit is reset to zero when the measurement is complete. r/w [0] 0x0 vertical measurement mode 0: free-running 1: one shot smeas_h_sel 0x0113 [7:4] reserved r/w [3:0] 0x0 select a horizontal sync, enable or clock for measurement. 0x0: analog hsync 0x1: hsync generated from llpll 0x2: sog from csync pin 0x3: nc 0x4: nc 0x5: nc 0x6: nc 0x7: nc 0x8: nc 0x9: tcon hsync 0xa: tcon data enable 0xb: inclk div1k 0xc: dotclk div1k 0xd-0xf: reserved table 9: sync measurement (sheet 3 of 8) register name addr mode bits default description
sync measurement ade3700 28/89 smeas_v_sel 0x0114 r/w [7:4] 0x0 selects a vertical signal for measurement of the high pulse width. 0x0: analog vsync 0x1: composite vsync 0x2: sog vsync 0x3: nc 0x4: nc 0x5: nc 0x6: nc 0x7: tcon vsync 0x8 - 0xf: reserved r/w [3:0] 0x0 selects a vertical signal for measurement of period and polarity. 0x0: analog vsync 0x1: composite vsync 0x2: nc 0x3: nc 0x4: nc 0x5: nc 0x6: nc 0x7: tcon vsync smeas_status_mask 0x0119 r/w [7] 0x0 mask bit for hsync polarity check 0: ignore 1: check r/w [6] 0x0 mask bit for vsync polarity check 0: ignore 1: check [5:4] reserved r/w [3] 0x0 mask bit for vert pulse width check 0: ignore 1: check r/w [2] 0x0 mask bit for h per v check 0: ignore 1: check r/w [1] 0x0 mask bit for h period check 0: ignore 1: check r/w [0] 0x0 mask bit for v period check 0: ignore 1: check smeas_h_num_lines 0x011a r/w [7:0] 0x0 number of lines to measure for horizontal period. valid range is 1 to 255. smeas_h_skip_l 0x011b r/w [7:0] 0x0 number of lines to skip before starting a horizontal measurement. the skip counter counts from the chosen vertical source and edge. [7:0] table 9: sync measurement (sheet 4 of 8) register name addr mode bits default description
29/89 ade3700 sync measurement smeas_h_skip_h 0x011c r/w [7:4] reserved [3:0] number of lines to skip before starting a horizontal measurement. the skip counter counts from the chosen vertical source and edge. [11:8] smeas_skew_ctrl 0x011d [7:3] 0x0 reserved r/w [2] 0x0 1 = delay vsync a number of xclks specified in smeas_delay_vsync [1] 0x0 reserved r/w [0] 0x0 write a rising edge to start the hv-skew measurement. smeas_skew_thres 0x011e r [7:0] 0x5 test skew limit in xclks. if the skew is less than this test limit, the smease_skew_status register will report an error condition. smeas_delay_vsync should be reprogrammed until the skew is large enough to prevent vcount ambiguity. smeas_delay_vsync 0x011f r/w [7:0] 0x3 number of xclks to delay vsync. smeas_ref_xk_per_h_l 0x0120 r/w [7:0] 0x0 reference value for xclks per horizontal event actual value = programmed value + 1 smeas_ref_xk_per_h_m 0x0121 r/w [7:0] 0x0 smeas_ref_xk_per_h_h 0x0122 r/w [7:0] 0x0 smeas_ref_xk_per_v_l 0x0123 r/w [7:0] 0x0 reference value for xclks per vertical event actual value = programmed value + 2 smeas_ref_xk_per_v_m 0x0124 r/w [7:0] 0x0 smeas_ref_xk_per_v_h 0x0125 r/w [7:0] 0x0 smeas_ref_h_per_v_l 0x0126 r/w [7:0] 0x0 reference value for horizontal events per vertical event smeas_ref_h_per_v_h 0x0127 r/w [7:0] 0x0 smeas_ref_xk_v_per_hi_l 0x0128 r/w [7:0] 0x0 reference value for vertical pulse width measurement result in xclks. actual value = programmed value + 1 smeas_ref_xk_v_per_hi_m 0x0129 r/w [7:0] 0x0 smeas_ref_xk_v_per_hi_h 0x012a r/w [7:0] 0x0 smeas_ref_polarity 0x012b [7:2] 0x0 reserved r/w [1] 0x0 reference value for hsync polarity. 0: active low 1: active high r/w [0] 0x0 reference value for vsync polarity. 0: active low 1: active high smeas_xk_htol_exp 0x012c r/w [7:4] 0x0 reserved [3:0] 0x0 horizontal tolerance; 2 n xclks smeas_xk_vtol_exp 0x012d [7:4] 0x0 reserved r/w [3:0] 0x0 vertical tolerance; 2 n xclks table 9: sync measurement (sheet 5 of 8) register name addr mode bits default description
sync measurement ade3700 30/89 smeas_hsync_vtol 0x012e [7:4] 0x0 reserved r/w [3:0] 0x0 horizontal per vertical tolerance, 2 n smeas_filtr_hs_width 0x012f r/w [7:0] 0x1 refer to register 0x0111 smeas_act_polling 0x013f [7:1] 0x0 reserved r [0] 0x0 toggle on activity status update in free- running mode. no function in one-shot mode. smeas_ana_act 0x0140 [7:5] 0x0 reserved r [4] 0x0 composite sync is active r [3] 0x0 vsync from sog separator is active r [2] 0x0 comp vsync from composite sync separator is active r [1] 0x0 analog hsync is active r [0] 0x0 analog vsync is active smeas_ana_stuck 0x0143 [7:5] 0x0 reserved r [4] 0x0 comp sync is stuck at 1(high)/0(low) r [3] 0x0 vsync from sog separator is stuck at 1(high)/0(low) r [2] 0x0 comp vsync from separator is stuck at 1(high)/0(low) r [1] 0x0 analog hsync is stuck at 1(high)/0(low) r [0] 0x0 analog vsync is stuck at 1(high)/0(low) smeas_xk_per_h_l 0x0146 r [7:0] 0x0 xclks per horizontal event - 1 smeas_xk_per_h_m 0x0147 r [7:0] 0x0 smeas_xk_per_h_h 0x0148 r [7:0] 0x0 smeas_xk_per_v_l 0x0149 r [7:0] 0x0 xclks per vertical event - 1 smeas_xk_per_v_m 0x014a r [7:0] 0x0 smeas_xk_per_v_h 0x014b r [7:0] 0x0 smeas_h_per_v_l 0x014c r [7:0] 0x0 horizontal events per vertical event smeas_h_per_v_h 0x014d r [7:0] 0x0 smeas_sk_v_hi_l 0x014e r [7:0] 0x0 vertical high time in xclks - 1 smeas_sk_v_hi_m 0x014f r [7:0] 0x0 smeas_sk_v_hi_h 0x0150 r [7:0] 0x0 smeas_timeout_status 0x0151 [7:2] 0x0 reserved r [1] 0x0 indicates that the horizontal measurement timed out. r [0] 0x0 indicates that the vertical measurement timed out. table 9: sync measurement (sheet 6 of 8) register name addr mode bits default description
31/89 ade3700 sync measurement smeas_status_range 0x0152 r [7] 0x0 in free-running mode any of the status bits can change at the end of each measurement. in one shot mode any of the status bits can change at the completion of the measurement. the meas_sticky_status bit is a bitwise or of bits[3:0] (before the bitwise or, the mask in smeas_status_mask is and in) and is sticky. the only way to reset it is for software to write a zero into this bit. this bit goes to the scaler to blank the scaler output. a write to this reg will reset it to 0. r [6] 0x0 indicates that one of the measured polarities does not match the reference value. r [5] 0x0 hsync (selected by smeas_h_sel) polarity. 0: active low 1: active high r [4] 0x0 vsync (selected by smeas_v_sel) polarity. 0: active low 1: active high r [3] 0x0 indicates that the vertical pulse width measurement exceeded the reference tolerance range. r [2] 0x0 indicates that the horizontal per vertical measurement exceeded the reference tolerance range. r [1] 0x0 indicates that the xclks per horizontal measurement exceeded the reference tolerance range. r [0] 0x0 indicates that the xclks per vertical measurement exceeded the reference tolerance range. smeas_meas_polling 0x0153 [7:2] 0x0 reserved r [1] 0x0 toggle on h meas free-running mode, at end of each meas. no function on one-shot mode. r [0] 0x0 toggle on v meas free-running mode, at end of each meas. no function on one-shot mode. smeas_skew_status 0x0154 [7:2] 0x0 reserved r [1] 0x0 0: hsync to vsync skew above threshold 1: hsync to vsync skew below threshold r [0] 0x0 0: skew measurement running 1: skew measurement finished table 9: sync measurement (sheet 7 of 8) register name addr mode bits default description
sync multiplexer (smux) ade3700 32/89 2.7 sync multiplexer (smux) the synchronization multiplexer (smux) selects a set of sync signals from the input sources and provides them to the scaler. it generates signals that are missing, depending on the capability. the mcu can select the output sync signals between the input sources and the generated signals. smeas_v_outof_rng 0x0155 r [7:0] 0x0 the number of times the xclks per vertical reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. smeas_h_outof_rng 0x0156 r [7:0] 0x0 the number of times the xclks per horizontal reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. smeas_hv_outof_rng 0x0157 r [7:0] 0x0 the number of times the horizontal per vertical reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. smeas_vhi_outof_rng 0x0158 r [7:0] 0x0 the number of times the vertical pulse width in xclks reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. smeas_hpol_outof_rng 0x0159 r [7:0] 0x0 the number of times the horizontal polarity reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. smeas_vpol_outof_rng 0x015a r [7:0] 0x0 the number of times the vertical polarity reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. figure 4: sync multiplexer block diagram table 9: sync measurement (sheet 8 of 8) register name addr mode bits default description output signal selector output signals signal generator hcount vcount internal signal selector h/v reference signals input signals odd data_valid hsync_internal vsync_internal enab_internal
33/89 ade3700 sync multiplexer (smux) 2.7.1 functional description the internal signal selector selects which of the input sources are to be used for the internal hsync, vsync and enab signals and is controlled by i2c register smux_ctrl0. the signal generator contains a horizontal and a vertical counter that are resynced using a horizontal and vertical reference signals respectively. the selection of the h/v references and the resync edge (either rising or falling) are programmed via smux_ ctrl1[3:0]. the signal generator requires both references to be defined, or else the counters will not run properly and the generated signals (other than venab) will be invalid. the output signal selector can be programmed to output any of the internal syncs, bypassed signals such as odd and data_valid, or the generated versions of all the signals (hsync, vsync, enab, odd, valid). vertical enable (venab) and clamp are always generated. the following table summarizes programming for typical modes. other sources (such as composite sync) are simple variations on these basic configurations. the programmed timing values of the generated signals (such as clamp) are relative to the reference signal and edge selected. for example, if the llk_hsync falling edge is selected as the horizontal reference, then all horizontal programming values are relative to it. three signals are generated using programmable set/reset values: clamp and the two components that make up the input enable signal (horizontal and vertical enables). the henab and venab signals define the video window that the scaler operates on. the difference between the reset and set quantities is the number of pixels (h) or lines (v) in the input image. clean wraparound is supported: the henab_set can be greater than the henab_rst. the clamp pulse should be located outside the active video area, i.e. both programmed values should be in the horizontal blanking region, typically in backporch of the incoming sync. all set/reset programming values for clamp and henab must be less than the input horizontal total. both set/reset programming values for venab must be less than the input vertical total. the updates for the enable registers can occur in four modes: 1. no shadowing 2. simple shadowing: updates occur when the upper byte of _rst is written 3. shadowing + blank update: updates occur only in the next blanking region after rst_u is written 4. shadowing + vblank update: updates occur in the next vblank region after rst_u is written. this mode also advances or retards the frame trigger to the scaler to prevent glitches. it takes one frame to write h and two frames to write the v-position. with large position changes, a glitch will show up. for small changes (e.g. 1) no glitch is created. the written position values are instantly available by read back, independent of shadow mode. the actual values being used by the hardware at a given time can also be read back using separate i2c addresses. table 10: sync multiplexer programming table mode valid inputs output source for hsync vsync enab valid odd venab clamp analog line lock llk_hsync llk_vsync llk llk gen gen na gen gen analog ext. clock vga_hsync llk_vsync testclk vga llk gen gen na gen gen
sync multiplexer (smux) ade3700 34/89 when hsync and/or vsync is generated (e.g. when enab is the only input), the relative position of the generated pulse can be set either before or after the reference edge between -128 and +127 pixels per line. 2.7.2 example adc input using line lock clock: omux_ctrl0 = 0x09 // select llk hsync and vsync omux_ctrl1 = 0x0f // choose incoming hsync and vsync as references, choose rising edges omux_ctrl2 = 0x0c // select the original hsyncs and vsyncs, along with the generated // enab and valid signals henab_set = hsync_width + hback_porch henab_rst = hsync_width + hback_porch + in_hpixel venab_set = vsync_width + vback_porch venab_rst = vsync_width + vback_porch + in_vpixel clamp_set = hsync_width + hback_porch + in_hpixel + 4 // clamp is turned on 4 after last pixel clamp_rst = hsync_width + hback_porch -4 // clamp is turned off 4 pixels before the 1st pixel table 11: sync multiplexer registers (sheet 1 of 4) register name addr mode bits default description smux_ctrl0 0x0200 [7:6] 0x0 reserved r/w [5:3] 0x0 vsync_internal select 0x0 = reserved 0x1 = llk/vga vsync 0x2 = reserved 0x3 = composite sync decoder 0x4 = reserved r/w [2:0] 0x0 hsync_internal select 0x0 = reserved 0x1 = llk synthesized hsync 0x2 = reserved 0x3 = raw vga hsync (jitter) 0x4 = reserved
35/89 ade3700 sync multiplexer (smux) smux_ctrl1 0x0201 r/w [7] 0x0 venab out select 0: derived from enab out 1: generated internally r/w [6] 0x0 0: simple reset of hcount by href 1: self reset of hcount, used when the chosen href is intermittent, e.g. generating hsync from henab source. r/w [5] 0x0 vsync_out invert r/w [4] 0x0 hsync_out invert r/w [3] 0x0 v_reference edge select 0: falling 1: rising r/w [2] 0x0 v_reference select 0: venab_generated 1: vsync_internal r/w [1] 0x0 h_reference edge select 0: falling 1: rising r/w [0] 0x0 h_reference select 0: enab_internal 1: hsync_internal smux_ctrl2 0x0202 r [7] 0x0 v_reference toggle output. r/w [6] 0x0 software odd set (for testing odd params on the bench) r/w [5:4] 0x0 odd_out select 0x0: reserved 0x1: vsync toggle 0x2: smux_ctrl2[6] 0x3: reserved r/w [3] 0x0 valid_out select 0: reserved 1: valid_generated r/w [2] 0x0 enab_out select 0: enab_internal 1: enab_generated r/w [1] 0x0 vsync_out select 0: vsync_internal 1: hsync_generated r/w [0] 0x0 hsync_out select 0: hsync_internal 1: hsync_generated table 11: sync multiplexer registers (sheet 2 of 4) register name addr mode bits default description
sync multiplexer (smux) ade3700 36/89 smux_ctrl3 0x0203 r [7:6] venab pending state 0x0: idle 0x1: venab pending frame 1 0x2: venab pending frame 2 wait until 0 to write venab again if in henab or venab shadow mode. r [5] henab pending [4] reserved r/w [3:2] 0x0 vtrigger reference 2'bx0: trigger ref = venab 2'b01: last pixel w/ anti-glitch 2'b11: first pixel w/ anti-glitch anti-glitch modes work only with venab shadow mode. first/last pixel must be consistent with out_seq in this mode. r/w [1:0] 0x0 0x0: no shadow 0x1: simple shadow. when henab_rst_u is written, henab_set_l, henab_set_u, henab_rst_l take effect. when venab_rst_u is written, venab_set_l, venab_set_u, venab_rst_l take effect. 0x2: henab shadow. wait for next available blank period to update positions after henab_rst_u or venab_rst_u is written. 0x3: venab shadow. wait for next available vblank period to update positions after henab_rst_u or venab_rst_u is written. venab update takes two frames. state can be watched in ctrl3[7:5]. smux_clamp_set_l 0x0204 r/w [7:0] 0x0 adc clamp signal rising edge [11:0], relative to selected h reference signal, in inclks (pixels) smux_clamp_set_u 0x0205 r/w [3:0] 0x0 adc clamp signal msbs smux_clamp_rst_l 0x0206 r/w [7:0] 0x0 adc clamp falling edge smux_clamp_rst_u 0x0207 r/w [3:0] 0x0 adc clamp falling edge smux_henab_set_l 0x0208 r/w [7:0] 0x0 horizontal enable start [11:0] (left edge of image) relative to the selected h reference edge in inclks (pixels) henab _set_u 0x0209 r/w [3:0] 0x0 horizontal enable start msbs henab _rst_l 0x020a r/w [7:0] 0x00 horizontal enable end lsbs henab _rst_u 0x020b r/w [3:0] 0x0 horizontal enable end msbs venab_set_l 0x020c r/w [7:0] 0x00 vertical enable start (top edge of image) relative to the selected vertical reference edge in lines venab _set_u 0x020d r/w [3:0] 0x0 vertical enable start msbs venab _rst_l 0x020e r/w [7:0] 0x00 vertical enable end lsbs venab _rst_u 0x020f r/w [3:0] 0x0 vertical enable end msbs table 11: sync multiplexer registers (sheet 3 of 4) register name addr mode bits default description
37/89 ade3700 data multiplexer 2.8 data multiplexer the data multiplexer provides the following functions: l debug modes (e.g. bit order swap, color swap) hsync_phase 0x0210 r/w [7:0] 0x00 number of horizontal pixels/inclks that the generated hsync edge is from the reference edge. 2s complement [-128,127] vsync_phase 0x0211 r/w [7:0] 0x00 number of vertical lines that the generated vsync edge is from the reference edge. 2s complement [-128,127] henab_set_hw_l 0x0212 r [7:0] actual value used by hardware post shadowing. henab _set_hw _u 0x0213 r [3:0] actual value used by hardware post shadowing. henab _rst_hw _l 0x0214 r [7:0] actual value used by hardware post shadowing. henab _rst_hw _u 0x0215 r [3:0] actual value used by hardware post shadowing. venab_set_hw _l 0x0216 r [7:0] actual value used by hardware post shadowing. venab _set_hw _u 0x0217 r [3:0] actual value used by hardware post shadowing. venab _rst_hw _l 0x0218 r [7:0] actual value used by hardware post shadowing. venab _rst_hw _u 0x0219 r [3:0] actual value used by hardware post shadowing. table 12: data mux registers register name addr. mode bits default description dmux_chansel 0x0280 [7] 0x0 reserved r/w [6] 0x0 0: normal 1: msb/lsb byte flip r/w [5:3] 0x0 if enabled by [2] 0x0: reserved 0x1: r & g bytes are swapped 0x2: b & g bytes are swapped 0x3: r => g, g => b, b => r 0x4: r & b bytes are swapped 0x5: r => b, g => r, b => g 0x0, 0x6-0x7: reserved r/w [2] 0x0 0: normal 1: enable color swap r/w [1:0] 0x0 video source select 0x0: adc data 0x1: nc 0x2: nc 0x3: for test only table 11: sync multiplexer registers (sheet 4 of 4) register name addr mode bits default description
data measurement (dmeas) ade3700 38/89 2.9 data measurement (dmeas) the data measurement (dmeas) module measures several characteristics of the data and sync signals. data measurements are taken over a programmable window as defined by an upper left (mix_x, min_y) and a lower right (max_x, max_y), which may be the whole frame. measurements are programmable either per color channel or over all color channels. this module computes all measurements of sync and data format that are done in the inclk domain. the sync measurement module does measurements in the xclk domain. the inclks per de measurement does not use the window feature. it measures the number of inclk per de and returns the result for every line. all unused or reserved bits will return as zero. windows are relative to sync pulses. a window defined from (0,0) - (0xfff, 0xfff) would go from sync to sync. the reference edge to use, rising or falling, is also programmable per x and y coordinates. smux should be configured to provide a positive polarity sync to the dmeas block. all window enables are reset to 0 and will always be reset on the rising or falling edge of the sync pulse. most algorithms can be run over separate or all color channels. most algorithms also contain a threshold value to zero out noise and/or amplify edges. algorithm, color, threshold, or window control changes are accepted at the end of a valid measurement so that they do not affect the current measurement in progress. software can request measurements in one of two ways: 1. all measurements, except de_size, are performed in one-shot mode, which is synchronous in respect the microcontroller. 2. the de_size measurement can be set either to one-shot or free-running modes. free- running mode is asynchronous in respect to the microcontroller. in one-shot mode , the block should indicate that the measurement is valid through an auto clear of the start condition. in free-running mode , the block should indicate that the measurement is valid through a polling bit. in free-running mode, a freeze bit is provided to freeze the results. measurements still continue with the polling bit active, however, they are not updated if the freeze bit is set. 2.9.1 edge intensity the edge intensity measurement is the sum of the absolute value of the delta between adjacent pixels. a programmable threshold is applied to zero out noise and amplify edges. equation: delta_val = abs(pixela - pixelb) - threshold; delta_val = delta_val < 0? 0: delta_val; sum += delta_val; for all 3 color channels: sum += delta_val on red channel + delta_val on green channel + delta_val on blue channel 2.9.2 pixel sum the pixel sum is the sum of all selected pixels for either a specific color channel or all color channels within the window specified. 2.9.3 minimum/maximum pixel this function reports the minimum and maximum pixel found within the specified window.
39/89 ade3700 data measurement (dmeas) 2.9.4 pixel cumulative distribution (pcd) the pixel cumulative distribution (pcd) function reports the total number of pixels greater than (or less than) a programmable threshold. to switch between pixels greater than or pixels less than the threshold, a control bit is provided in the dmm_mode register when requesting a measurement. 2.9.5 horizontal position the horizontal position measures the start and end of video data in inclks clock cycles relative to the posedge of hsync. the data horizontal start is defined as the number of inclks clock cycles between posedge of hsync and the first data pixel. first data pixel is either: 1. first pixel greater than the programmable threshold value 2. first pixel with the absolute value (current pixel - previous pixel) is greater than the programmable threshold value the data horizontal end is defined as the number of inclks clock cycles between posedge of hsync and the last data pixel plus one. the search for the last pixels ends at the end of a window. last data pixel plus one is either: 1. pixel after the last pixel that is greater than the programmable threshold value 2. last pixel with the absolute value (current pixel - previous pixel) is greater than the programmable threshold value to switch between the two threshold methods used in the first and last pixel, a control bit is provided in the dmm_mode register when requesting a measurement. the first and last pixels are measured for each line, and the earliest first and latest last for the selected pixel area are reported out at the end of the measurement. the intention is for last data pixel plus one minus first data pixel is to equal the horizontal width of the video format. 2.9.6 vertical position the vertical position measures the start and end of video data in hsyncs relative to the posedge of vsync. the data vertical start is defined as the number of hsyncs signals between the positive edge of the vsync signal and the first data pixel line. first data pixel line definition is the first line with at least one pixel that is greater then the programmable threshold. the data vertical end is defined as the number of hsyncs between posedge of vsync and the first blanking line after data plus one. the first blanking line is detected then confirmed that each subsequent line contains no data pixels. the confirmation of the first blanking line measurement ends at the posedge of vsync. the first blanking line after data definition is the row after the last row with at least one pixel greater than the programmable threshold. the first and last data pixel lines are measured within a frame and the earliest first and latest last for the selected pixel area are reported out at the end of the measurement. the intention is for data vertical end plus one minus data vertical start is to equal the vertical height of the video format.
data measurement (dmeas) ade3700 40/89 2.9.7 de size the de size measures the number of inclks clock cycles per data enable. it is useful for dvi inputs to exactly measure the input image horizontal size. at the end of the measurement (de falling edge), the measured value is compared to a programmed expected value a programmed threshold. if the expected value is within the threshold, the de_size_mismatch flag is not set. if the measured size is outside of the threshold, the de_size_mismatch flag is set. in free-running mode, the results are updated every line. the de_size_mismatch flag is set at de falling edge and reset at de rising edge. in one-shot mode, the results are updated once and stay that way until they are cleared by software. the de_size_mismatch flag can only be cleared when the reset flag bit is set by software. table 13: dmeas output register mapping alg_sel = 00 alg_sel = 01 alg_sel = 10 alg_sel = 11 dmeas_data_0 edge_out [7:0] min_out [7:0] hpos_min [7:0] de_size_out [ 7:0] dmeas_data_1 edge_out [15:8] max_out [7:0] hpos_min [11:8] de_size_out [15: 8] dmeas_data_2 edge_out [23:16] pcd_out [7:0] hpos_max [7:0] de_mismatch_fla g dmeas_data_3 edge_out [31:24] pcd_out [15:8] hpos_max [11:8] 8h00 dmeas_data_4 psum_out [7:0] pcd_out [23:16] vpos_min [7:0] 8h0 0 dmeas_data_5 psum_out [15:8] 8h00 vpos_min [11:8] 8h00 dmeas_data_6 psum_out [23:16] 8h00 vpos_max [7:0] 8 h00 dmeas_data_7 psum_out [31:24] 8h00 vpos_max [11:8] 8 h00 table 14: data measurement registers (sheet 1 of 3) register name addr mode bits default description dmeas_aec_ctrl 0x0900 [7:6] 0x0 color select 00: all 01: red 10: green 11: blue r/w [5] 0x0 vsync edge select 0: rising edge 1: falling edge r/w [4] 0x0 hsync edge select 0: rising edge 1: falling edge r/w [3] 0x0 interlace mode enable r/w [2] 0x0 0: use data valid (tv mode only) 1: use data enable for data valid r/w [1:0] 0x0 algorithm select 00 = edge intensity & pixel sum 01 = min / max & pcd 10 = h position and v position 11 = de size
41/89 ade3700 data measurement (dmeas) dmeas_mode_ctrl 0x0901 r/w [7] 0x0 reset the de mismatch flag r/w [6] 0x0 de_freeze enable r/w [5] 0x0 de_one shot mode enable r/w [4] 0x0 0: listen to odd frame only 1: listen to even frame only r/w [3] 0x0 threshold mode bit r/w [1] 0x0 polling bit r/w [0] 0x0 data measurement start dmeas_threshold 0x0902 r/w [7:0] 0x0 threshold value for selected algorithm dmeas_win_min_x_l 0x0903 r/w [7:0] 0x0 min. x window [7:0] (bits[3:0] read back 0. dmeas_win_min_x_h 0x0904 [7:4] reserved r/w [3:0] min. x window [11:8] (relative to hsync) dmeas_win_max_x_l 0x0905 r/w [7:0] 0xfff max. x window [7:0] (bits[3:0] read back 0. dmeas_win_max_x_h 0x0906 [7:4] reserved r/w [3:0] max. x window [11:8] relative to hsync, must be less than input horizontal total (llk_linelen for analog input). dmeas_win_min_y_l 0x0907 r/w [7:0] 0x0 min. y window [7:0] (bits[3:0] read back 0. dmeas_win_min_y_h 0x0908 [7:4] reserved r/w [3:0] min. y window [11:8] (relative to vsync) dmeas_win_max_y_l 0x0909 r/w [7:0] 0xfff max. y window [7:0] (bits[3:0] read back 0. dmeas_win_max_y_h 0x090a [7:4] reserved r/w [3:0] max. y window [11:8] (relative to vsync) dmeas_de_ref_l 0x090b r/w [7:0] 0x0 de_size expected result [7:0] dmeas_de_ref_l 0x090c r/w [7:0] 0x0 de_size expected result [15:8] dmeas_de_tol 0x090d r/w [7:0] 0x0 de_tolerance value dmeas_data_0 0x090e r [7:0] 0x0 for details, refer to table 13 . dmeas_data_1 0x090f r [7:0] 0x0 dmeas_data_2 0x0910 r [7:0] 0x0 dmeas_data_3 0x0911 r [7:0] 0x0 dmeas_data_4 0x0912 r [7:0] 0x0 dmeas_data_5 0x0913 r [7:0] 0x0 dmeas_data_6 0x0914 r [7:0] 0x0 dmeas_data_7 0x0915 r [7:0] 0x0 table 14: data measurement registers (sheet 2 of 3) register name addr mode bits default description
lcd scaler ade3700 42/89 2.10 lcd scaler the lcd scaler module resizes images from one resolution to another. it employs a 3x3 non- separable scaling filter which performs a dot product of the input pixel values with a weighting vector that is computed from the chosen filtering function. to sharpen text without introducing excessive artifacts, the output pixel's contrast level is adjusted based on the context value measured over a 3x3 grid in the relevant area of the source image. for proper scaler operation, the sclk frequency must be set greater than the max of dclk and in_hpixel x dclk_freq / (dest_hpixel x pixel_avg). dmeas_scr_pad_0 0x0934 r [7:0] 0x0 scratch pad registers dmeas_scr_pad_1 0x0916 r/w [7:0] dmeas_scr_pad_2 0x0917 r/w [7:0] dmeas_scr_pad_3 0x0918 r/w [7:0] dmeas_scr_pad_4 0x0919 r/w [7:0] dmeas_scr_pad_5 0x091a r/w [7:0] dmeas_scr_pad_6 0x091b r/w [7:0] dmeas_scr_pad_7 0x091c r/w [7:0] dmeas_scr_pad_8 0x091e r/w [7:0] dmeas_scr_pad_9 0x091f r/w [7:0] dmeas_scr_pad_10 0x0920 r/w [7:0] dmeas_scr_pad_11 0x0921 r/w [7:0] dmeas_scr_pad_12 0x0922 r/w [7:0] dmeas_scr_pad_13 0x0923 r/w [7:0] dmeas_scr_pad_14 0x0924 r/w [7:0] dmeas_scr_pad_15 0x0925 r/w [7:0] table 15: lcd scaler registers (sheet 1 of 3) register name addr mode bits default description scl_src_hpix_l 0x0a01 r/w [7:0] 0x0 input horizontal resolution bits [3:0] must be set to zero. scl_src_hpix_h 0x0a02 r/w [7:0] scl_src_vpix_l 0x0a03 r/w [7:0] 0x0 input vertical resolution bits[3:0] must be set to 0. scl_src_vpix_h 0x0a04 r/w [7:0] scl_scalefach_l 0x0a05 r/w [7:0] 0x0 17-bit horizontal scale factor = (in_hpixel << 16) / dest_hpixel + 0.5 scl_scalefach_m 0x0a06 r/w [7:0] 0x0 scl_scalefach_h 0x0a07 r/w [0] 0x0 scl_scalefacv_l 0x0a08 r/w [7:0] 0x0 16-bit vertical scale factor = (in_vpixel << 15) / dest_vpixel + 0.5 scl_scalefacv_h 0x0a09 r/w [7:0] 0x0 table 14: data measurement registers (sheet 3 of 3) register name addr mode bits default description
43/89 ade3700 lcd scaler scl_orighpos_0 0x0a0a r/w [7:0] 0x0 2's complement, signed number 27-bit horizontal position of the first output pixel =(-dest_hpos * scalefactor_h) >> 5 scl_orighpos_1 0x0a0b r/w [7:0] 0x0 scl_orighpos_2 0x0a0c r/w [7:0] 0x0 scl_orighpos_3 0x0a0d rw [2:0] 0x0 scl_origvpos_e_0 0x0a0e r/w [7:0] 0x0 2's complement, signed number 27-bit vertical position of the first output pixel of the even frame = (-dest_vpos_e * scalefactor_v) >> 5 scl_origvpos_e_1 0x0a0f r/w [7:0] scl_origvpos_e_2 0x0a10 r/w [7:0] 0x0 scl_origvpos_e_3 0x0a11 r/w [2:0] scl_thres_slope 0x0a16 [7:6] 0x0 reserved r/w [5:0] 0x28 slope of the contrast amplification function scl_thres_offset_l 0x0a17 r/w [7:0] 0x40 offset of the contrast amplification function [7:0] scl_thres_offset_h 0x0a18 [7:2] 0x0 reserved r/w [1:0] 0x2 offset of the contrast amplification function [9:8] scl_cbbypass 0x0a19 r/w [7:2] 0x0 reserved [1] 0x0 0: normal 1: tcon control of contrast amplification r/w [0] 0x0 0: contrast amplification enabled 1: bypass contrast amplification scl_con_cal_sel 0x0a1a [7:1] reserved r/w [0] 0x0 0: context = max of rgb pk-pk 1: context = sum of rgb pk-pk scl_testcon 0x0a1b [7:2] 6-bit contrast amplification test data r/w [1:0] 0x0 0x0, 0x3: normal 0x1: force input data into the contrast amplification function to bits [7:2] 0x2: force the output context data to be bits [5:2] scl_lut1 0x0a1c r/w [7:0] 0xfa sigmoidal function lut entry 1, 8-bit 2s complement scl_lut2 0x0a1d r/w [7:0] 0xf7 sigmoidal function lut entry 2, 8-bit 2s complement scl_lut3 0x0a1e r/w [7:0] 0xf7 sigmoidal function lut entry 3, 8-bit 2s complement scl_lut4 0x0a1f r/w [7:0] 0xfc sigmoidal function lut entry 4, 8-bit 2s complement scl_lut5 0x0a20 r/w [7:0] 0x2 sigmoidal function lut entry 5, 8-bit 2s complement scl_lut6 0x0a21 r/w [7:0] 0x0d sigmoidal function lut entry 6, 8-bit 2s complement table 15: lcd scaler registers (sheet 2 of 3) register name addr mode bits default description
lcd scaler ade3700 44/89 scl_lut7 0x0a22 r/w [7:0] 0x17 sigmoidal function lut entry 7, 8-bit 2s complement scl_lut8 0x0a23 r/w [7:0] 0x21 sigmoidal function lut entry 8, 8-bit 2s complement scl_lut9 0x0a24 r/w [7:0] 0x28 sigmoidal function lut entry 9, 8-bit 2s complement scl_lut10 0x0a25 r/w [7:0] 0x2c sigmoidal function lut entry 10, 8-bit 2s complement scl_lut11 0x0a26 r/w [7:0] 0x2c sigmoidal function lut entry 11, 8-bit 2s complement scl_lut12 0x0a27 r/w [7:0] 0x28 sigmoidal function lut entry 12, 8-bit 2s complement scl_lut13 0x0a28 r/w [7:0] 0x21 sigmoidal function lut entry 13, 8-bit 2s complement scl_lut14 0x0a29 r/w [7:0] 0x17 sigmoidal function lut entry 14, 8-bit 2s complement scl_lut15 0x0a2a r/w [7:0] 0x0c sigmoidal function lut entry 15, 8-bit 2s complement scl_bgcolor_r 0x0a2b r/w [7:0] 0x0 red component of background color scl_bgcolor_g 0x0a2c r/w [7:0] 0x0 green component of background color scl_bgcolor_b 0x0a2d r/w [7:0] 0x0 blue component of background color scl_bcolor_ctrl 0x0a2e r/w [7] 0x0 0: normal 1: force image to background color r/w [6] 0x0 top & bottom border control 0: pixel replicating 1: background color blending r/w [5] 0x0 left & right border control: 0: pixel replicating 1: background color blending r/w [4] 0x0 force output data as described in bit [1] when the maximum output vertical is reached. r/w [3] 0x0 force output data as described in bit [1] when an abnormal condition is detected by the sync measurement module. r/w [2] 0x0 when the scaler is not running, force the output data to black if this bit is 0 or to the background color if the bit is 1. r/w [1] 0x0 if an abnormality is detected in the sync measurement module or if the maximum output vertical total has been reached, force the output data to black if this bit is 0 or to white if this bit is 1. r/w [0] 0x0 during blanking, force output data to black if this bit is 0 or to the background color if this bit is 1. table 15: lcd scaler registers (sheet 3 of 3) register name addr mode bits default description
45/89 ade3700 output sequencer 2.11 output sequencer the output sequencer module synchronizes timing for the output video interface. it allows sufficient flexibility to support a broad range of smart panel applications as well using the output timing controller (tcon) module, refer to section 2.12 for more details. the timing unit is based on horizontal and vertical counters, which are locked with the input video stream. 2.11.1 frame synchronization due to the limited pixel memory of the chip, the output active video needs to be perfectly synchronized with the input active video. this mode of operation is called frame lock . 2.11.2 timing unit the timing unit consists of a 12-bit horizontal and 12-bit vertical counter. it is synchronized with the input video stream. 2.11.3 signal generation the signal generation unit can generate all fixed control signals like hsync, vsync and data enable as well as those required to run the internal data path. the fixed control signals appear on the figure 5: output sequencer and timing controller block diagram figure 6: frame lock operation i 2 c interface timing unit delay vert_start horizontal vertical signal generation fixed (osq) programmable (tcon) hs, vs, den tcon [o:13]
output sequencer ade3700 46/89 alternate output sync pins (ahs, aus, ade) for applications that do not require the more sophisticated timing control provided by the programmable tcon module. table 16: output sequencer registers (sheet 1 of 2) register name addr mode bits default description osq_control 0x0bc1 r [7] out_vmax detected, sticky bit r/w [6] 0x0 out_vmax detect reset r/w [5] 0x0 interlace enable r/w [4] 0x0 fractional line extend 0: +1 1: +2 r/w [3] 0x0 frame lock reference 0: last input pixel 1: first input pixel r/w [2] 0x0 frame lock selection 0: last line variable 1: fixed line length r [1] shutdown ready - current frame has completed, panel can now be shut down r/w [0] 0x0 run sequencer when 1, otherwise stop at the end of the frame and set shutdown ready flag (bit [1]) osq_clock_frac 0x0bc2 r/w [7:0] 0x0 the fraction of lines (/256) that are extended osq_out_htotal_l 0x0bc3 r/w [7:0] 0x0 nominal output horizontal total [7:0] osq_out_htotal_h 0x0bc4 [7:4] reserved r/w [3:0] 0x0 nominal output horizontal total [11:8] osq_out_vtotal_min_l 0x0bc5 r/w [7:0] 0x0 minimum output vertical total, used to rearm for vert_enab trigger [7:0] osq_out_vtotal_min_h 0x0bc6 [7:4] reserved r/w [3:0] 0x0 minimum output vertical total, used to rearm for vert_enab triggers [11:8] osq_vtotal_max_l 0x0bc7 r/w [7:0] 0x0 maximum output vertical total, prevents panel burn with loss of vert_enab trigger [7:0] osq_vtotal_max_h 0x0bc8 [7:4] reserved r/w [3:0] 0x0 maximum output vertical total, prevents panel burn with loss of vert_enab triggers [11:8] osq_verten_dly_e_l 0x0bc9 r/w [7:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, even and non-interlaced modes [15:0] osq_verten_dly_e_m 0x0bca r/w [7:0] 0x0 osq_verten_dly_e_h 0x0bcb [7:4] reserved r/w [3:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, even and non-interlaced [19:16]
47/89 ade3700 output sequencer osq_verten_dly_o_l 0x0bcc r/w [7:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, odd frame in interlace mode only [15:0] osq_verten_dly_o_m 0x0bcd r/w [7:0] 0x0 osq_verten_dly_o_h 0x0bce [7:4] 0x0 reserved r/w [3:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, odd frame in interlace mode only [19:16] osq_vsync_set_l 0x0bcf r/w [7:0] 0x0 vertical count at which vsync goes high [7:0] osq_vsync_set_h 0x0bd0 [7:4] 0x0 reserved r/w [3:0] 0x0 vertical count at which vsync goes high [11:8] osq_vsync_rst_l 0x0bd1 r/w [7:0] 0x0 vertical count at which vsync goes low [7:0] osq_vsync_rst_h 0x0bd2 [7:4] 0x0 reserved r/w [3:0] 0x0 vertical count at which vsync goes low [11:8] osq_hsync_set_l 0x0bd3 r/w [7:0] 0x0 horizontal count at which hsync goes high [7:0] osq_hsync_set_h 0x0bd4 [7:4] 0x0 reserved r/w [3:0] horizontal count at which hsync goes high [11:8] osq_hsync_rst_l 0x0bd5 r/w [7:0] 0x0 horizontal count at which hsync goes low [7:0] osq_hsync_rst_h 0x0bd6 [7:4] 0x0 reserved r/w [3:0] 0x0 horizontal count at which hsync goes low [11:8] osq_henab_set_l 0x0bd7 r/w [7:0] 0x0 horizontal count at which enab goes high [7:0] osq_henab_set_h 0x0bd8 [7:4] 0x0 reserved r/w [3:0] 0x0 horizontal count at which enab goes high [11:8] value must be greater than 0x01c osq_henab_rst_l 0x0bd9 r/w [7:0] 0x0 horizontal count at which enab goes low [7:0] osq_henab_rst_h 0x0bda [7:4] 0x0 reserved r/w [3:0] 0x0 horizontal count at which enab goes low [11:8] osq_venab_set_l 0x0bdb r/w [7:0] 0x0 vertical count at which enab goes high [7:0] osq_venab_set_h 0x0bdc [7:4] 0x0 reserved r/w [3:0] 0x0 vertical count at which enab goes high [11:8] osq_venab_rst_l 0x0bdd r/w [7:0] 0x0 vertical count at which enab goes low [7:0] osq_venab_rst_h 0x0bde [7:4] 0x0 reserved r/w [3:0] 0x0 vertical count at which enab goes low [11:8] osq_out_vcount 0x0bdf r [7:0] 0x0 vertical counter /16 indicating the current frame position table 16: output sequencer registers (sheet 2 of 2) register name addr mode bits default description
timing controller (tcon) ade3700 48/89 2.12 timing controller (tcon) the output timing controller module provides timing for smart panel applications and other applications that are sensitive to output synchronization timing. the timing unit is based on horizontal and vertical counters, which are locked with the output video stream. a set of programmable comparators provides all necessary time events to generate the signals for the driver interface. please refer to the programming tool users manual and to the using tcon outputs application note for more details. table 17: tcon registers (sheet 1 of 7) register name addr. mode bits default description tcon_control 0x0b00 [7:3] reserved r/w [2] 0x0 0: no tcon pipe delay matching 1: tcon pipe delay enabled (normal) r/w [1] 0x0 initialize srtds r/w [0] 0x0 enable tcon tcon_comp_0_l 0x0b10 r/w [7:0] 0x0 count comparison value [7:0] tcon_comp_0_h 0x0b11 r/w [7:5] reserved r/w [4] 0: horizontal count compare 1: vertical count compare r/w [3:0] count comparison value [11:8] tcon_comp_1_l 0x0b12 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_1_h 0x0b13 r/w [7:0] 0x0 tcon_comp_2_l 0x0b14 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_2_h 0x0b15 r/w [7:0] 0x0 tcon_comp_3_l 0x0b16 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_3_h 0x0b17 r/w [7:0] 0x0 tcon_comp_4_l 0x0b18 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_4_h 0x0b19 r/w [7:0] 0x0 tcon_comp_5_l 0x0b1a r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_5_h 0x0b1b r/w [7:0] 0x0 tcon_comp_6_l 0x0b1c r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_6_h 0x0b1d r/w [7:0] 0x0 tcon_comp_7_l 0x0b1e r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_7_h 0x0b1f r/w [7:0] 0x0 tcon_comp_8_l 0x0b20 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_8_h 0x0b21 r/w [7:0] 0x0 tcon_comp_9_l 0x0b22 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_9_h 0x0b23 r/w [7:0] 0x0
49/89 ade3700 timing controller (tcon) tcon_comp_10_l 0x0b24 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_10_h 0x0b25 r/w [7:0] 0x0 tcon_comp_11_l 0x0b26 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_11_h 0x0b27 r/w [7:0] 0x0 tcon_comp_12_l 0x0b28 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_12_h 0x0b29 r/w [7:0] 0x0 tcon_comp_13_l 0x0b2a r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_13_h 0x0b2b r/w [7:0] 0x0 tcon_comp_14_l 0x0b2c r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_14_h 0x0b2d r/w [7:0] 0x0 tcon_comp_15_l 0x0b2e r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_15_h 0x0b2f r/w [7:0] 0x0 tcon_comp_16_l 0x0b30 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_16_h 0x0b31 r/w [7:0] 0x0 tcon_comp_17_l 0x0b32 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_17_h 0x0b33 r/w [7:0] 0x0 tcon_comp_18_l 0x0b34 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_18_h 0x0b35 r/w [7:0] 0x0 tcon_comp_19_l 0x0b36 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_19_h 0x0b37 r/w [7:0] 0x0 tcon_comp_20_l 0x0b38 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_20_h 0x0b39 r/w [7:0] 0x0 tcon_comp_21_l 0x0b3a r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_21_h 0x0b3b r/w [7:0] 0x0 tcon_comp_22_l 0x0b3c r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_22_h 0x0b3d r/w [7:0] 0x0 tcon_comp_23_l 0x0b3e r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_23_h 0x0b3f r/w [7:0] 0x0 tcon_comp_24_l 0x0b40 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_24_h 0x0b41 r/w [7:0] 0x0 tcon_comp_25_l 0x0b42 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_25_h 0x0b43 r/w [7:0] 0x0 tcon_comp_26_l 0x0b44 r/w [7:0] 0x0 v to tcon_comp_0 for definition tcon_comp_26_h 0x0b45 r/w [7:0] 0x0 table 17: tcon registers (sheet 2 of 7) register name addr. mode bits default description
timing controller (tcon) ade3700 50/89 tcon_comp_27_l 0x0b46 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_27_h 0x0b47 r/w [7:0] 0x0 tcon_srtd_0 0x0b50 [7:4] 0x0 reserved r/w [3] 0x0 srtd initialization state r/w [2:0] 0x0 0x0: f (a&b,&c&d,0,0) 0x1: f (a&b,&c&d,0,0) 0x2: f (a&b,&c&d,0,0) 0x3: f (0,0,a&b,0) 0x4: f (0,0,0,a&b) 0x5: f (0,0,0,a|b) 0x6: f (0,0,0,a^b) 0x7: f (0,0,0,!(a&b)) where f(set, reset, toggle, dflop) is a programmable logic/flop element tcon_srtd_1 0x0b51 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_2 0x0b52 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_3 0x0b53 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_4 0x0b54 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_5 0x0b55 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_6 0x0b56 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_7 0x0b57 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_8 0x0b58 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_9 0x0b59 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_10 0x0b5a r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_11 0x0b5b r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_12 0x0b5c r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_13 0x0b5d r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_14 0x0b5e r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_15 0x0b5f r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_16 0x0b60 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_17 0x0b61 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_18 0x0b62 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_19 0x0b63 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_20 0x0b64 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_21 0x0b65 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_22 0x0b66 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_23 0x0b67 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_24 0x0b68 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_25 0x0b69 r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. table 17: tcon registers (sheet 3 of 7) register name addr. mode bits default description
51/89 ade3700 timing controller (tcon) tcon_srtd_26 0x0b6a r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_27 0x0b6b r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_28 0x0b6c r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_29 0x0b6d r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_30 0x0b6e r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_srtd_31 0x0b6f r/w [7:0] 0x0 refer to tcon_srtd_0 for definition. tcon_x_0 0x0b80 [7:6] reserved r/w [5:0] 0x0 input selection for srtd_0.a tcon_x_1 0x0b81 r/w [7:0] 0x0 input selection for srtd_0.b (refer to table 18 for definition) tcon_x_2 0x0b82 r/w [7:0] 0x0 input selection for srtd_1.a (refer to table 18 for definition) tcon_x_3 0x0b83 r/w [7:0] 0x0 input selection for srtd_1.b (refer to table 18 for definition) tcon_x_4 0x0b84 r/w [7:0] 0x0 input selection for srtd_2.a (refer to table 18 for definition) tcon_x_5 0x0b85 r/w [7:0] 0x0 input selection for srtd_2.b (refer to table 18 for definition) tcon_x_6 0x0b86 r/w [7:0] 0x0 input selection for srtd_3.a (refer to table 18 for definition) tcon_x_7 0x0b87 r/w [7:0] 0x0 input selection for srtd_3.b (refer to table 18 for definition) tcon_x_8 0x0b88 r/w [7:0] 0x0 input selection for srtd_4.a (refer to table 18 for definition) tcon_x_9 0x0b89 r/w [7:0] 0x0 input selection for srtd_4.b (refer to table 18 for definition) tcon_x_10 0x0b8a r/w [7:0] 0x0 input selection for srtd_5.a (refer to table 18 for definition) tcon_x_11 0x0b8b r/w [7:0] 0x0 input selection for srtd_5.b (refer to table 18 for definition) tcon_x_12 0x0b8c r/w [7:0] 0x0 input selection for srtd_6.a (refer to table 18 for definition) tcon_x_13 0x0b8d r/w [7:0] 0x0 input selection for srtd_6.b (refer to table 18 for definition) tcon_x_14 0x0b8e r/w [7:0] 0x0 input selection for srtd_7.a (refer to table 18 for definition) tcon_x_15 0x0b8f r/w [7:0] 0x0 input selection for srtd_7.b (refer to table 18 for definition) tcon_x_16 0x0b90 r/w [7:0] 0x0 input selection for srtd_8.a (refer to table 18 for definition) tcon_x_17 0x0b91 r/w [7:0] 0x0 input selection for srtd_8.b (refer to table 18 for definition) table 17: tcon registers (sheet 4 of 7) register name addr. mode bits default description
timing controller (tcon) ade3700 52/89 tcon_x_18 0x0b92 r/w [7:0] 0x0 input selection for srtd_9.a (refer to table 18 for definition) tcon_x_19 0x0b93 r/w [7:0] 0x0 input selection for srtd_9.b (refer to table 18 for definition) tcon_x_20 0x0b94 r/w [7:0] 0x0 input selection for srtd_10.a (refer to table 18 for definition) tcon_x_21 0x0b95 r/w [7:0] 0x0 input selection for srtd_10.b (refer to table 18 for definition) tcon_x_22 0x0b96 r/w [7:0] 0x0 input selection for srtd_11.a (refer to table 18 for definition) tcon_x_23 0x0b97 r/w [7:0] 0x0 input selection for srtd_11.b (refer to table 18 for definition) tcon_x_24 0x0b98 r/w [7:0] 0x0 input selection for srtd_12.a (refer to table 18 for definition) tcon_x_25 0x0b99 r/w [7:0] 0x0 input selection for srtd_12. (refer to table 18 for definition) tcon_x_26 0x0b9a r/w [7:0] 0x0 input selection for srtd_13.a (refer to table 18 for definition) tcon_x_27 0x0b9b r/w [7:0] 0x0 input selection for srtd_13.b (refer to table 18 for definition) tcon_x_28 0x0b9c r/w [7:0] 0x0 input selection for srtd_14.a (refer to table 18 for definition) tcon_x_29 0x0b9d r/w [7:0] 0x0 input selection for srtd_14.b (refer to table 18 for definition) tcon_x_30 0x0b9e r/w [7:0] 0x0 input selection for srtd_15.a (refer to table 18 for definition) tcon_x_31 0x0b9f r/w [7:0] 0x0 input selection for srtd_15.b (refer to table 18 for definition) tcon_x_32 0x0ba0 r/w [7:0] 0x0 input selection for srtd_16.a (refer to table 18 for definition) tcon_x_33 0x0ba1 r/w [7:0] 0x0 input selection for srtd_16.b (refer to table 18 for definition) tcon_x_34 0x0ba2 r/w [7:0] 0x0 input selection for srtd_17.a (refer to table 18 for definition) tcon_x_35 0x0ba3 r/w [7:0] 0x0 input selection for srtd_17.b (refer to table 18 for definition) tcon_x_36 0x0ba4 r/w [7:0] 0x0 input selection for srtd_18.a (refer to table 18 for definition) tcon_x_37 0x0ba5 r/w [7:0] 0x0 input selection for srtd_18.b (refer to table 18 for definition) tcon_x_38 0x0ba6 r/w [7:0] 0x0 input selection for srtd_19.a (refer to table 18 for definition) tcon_x_39 0x0ba7 r/w [7:0] 0x0 input selection for srtd_19.b (refer to table 18 for definition) table 17: tcon registers (sheet 5 of 7) register name addr. mode bits default description
53/89 ade3700 timing controller (tcon) tcon_x_40 0x0ba8 r/w [7:0] 0x0 input selection for srtd_20.a (refer to table 18 for definition) tcon_x_41 0x0ba9 r/w [7:0] 0x0 input selection for srtd_20.b (refer to table 18 for definition) tcon_x_42 0x0baa r/w [7:0] 0x0 input selection for srtd_21.a (refer to table 18 for definition) tcon_x_43 0x0bab r/w [7:0] 0x0 input selection for srtd_21.b (refer to table 18 for definition) tcon_x_44 0x0bac r/w [7:0] 0x0 input selection for srtd_22.a (refer to table 18 for definition) tcon_x_45 0x0bad r/w [7:0] 0x0 input selection for srtd_22.b (refer to table 18 for definition) tcon_x_46 0x0bae r/w [7:0] 0x0 input selection for srtd_23.a (refer to table 18 for definition) tcon_x_47 0x0baf r/w [7:0] 0x0 input selection for srtd_23.b (refer to table 18 for definition) tcon_x_48 0x0bb0 r/w [7:0] 0x0 input selection for srtd_24.a (refer to table 18 for definition) tcon_x_49 0x0bb1 r/w [7:0] 0x0 input selection for srtd_24.b (refer to table 18 for definition) tcon_x_50 0x0bb2 r/w [7:0] 0x0 input selection for srtd_25.a (refer to table 18 for definition) tcon_x_51 0x0bb3 r/w [7:0] 0x0 input selection for srtd_25.b (refer to table 18 for definition) tcon_x_52 0x0bb4 r/w [7:0] 0x0 input selection for srtd_26.a (refer to table 18 for definition) tcon_x_53 0x0bb5 r/w [7:0] 0x0 input selection for srtd_26.b (refer to table 18 for definition) tcon_x_54 0x0bb6 r/w [7:0] 0x0 input selection for srtd_27.a (refer to table 18 for definition) tcon_x_55 0x0bb7 r/w [7:0] 0x0 input selection for srtd_27.b (refer to table 18 for definition) tcon_x_56 0x0bb8 r/w [7:0] 0x0 input selection for srtd_28.a (refer to table 18 for definition) tcon_x_57 0x0bb9 r/w [7:0] 0x0 input selection for srtd_28.b (refer to table 18 for definition) tcon_x_58 0x0bba r/w [7:0] 0x0 input selection for srtd_29.a (refer to table 18 for definition) tcon_x_59 0x0bbb r/w [7:0] 0x0 input selection for srtd_29.b (refer to table 18 for definition) tcon_x_60 0x0bbc r/w [7:0] 0x0 input selection for srtd_30.a (refer to table 18 for definition) tcon_x_61 0x0bbd r/w [7:0] 0x0 input selection for srtd_30.b (refer to table 18 for definition) table 17: tcon registers (sheet 6 of 7) register name addr. mode bits default description
pattern generator ade3700 54/89 2.13 pattern generator the integrated pattern generator gives the ability to display a set of graphic patterns to help debugging systems and test lcd panels. it is located ahead of the color management block, so all generated colors are subject to further transforms. the screen can be split into a programmable grid of up to 8x8 areas. in each of these areas, it is possible to display one of two independent programmable patterns. 2.13.1 screen split a set of eight grid registers grid0 - grid7 with eight bits each represents a block map of the grid of 8x8 blocks. each bit of the grid registers represents one rectangular (gridx)x( gridy) block of pixels which covers the lcd screen display area. within these registers, a 0 selects pattern 0 (defined below) and a 1 selects pattern 1. all cells have the same size, defined by one horizontal and one vertical grid block size registers gridx and gridy . when the programmed block size is such that the complete 8x8 grid is larger than the total screen area, only the blocks or part of blocks that are included in the output screen space are rendered. the 8x8 block set is upper left justified, such that all blocks on the right and bottom sides that are outside of the total display area are not rendered. tcon_x_62 0x0bbe r/w [7:0] 0x0 input selection for srtd_31.a (refer to table 18 for definition) tcon_x_63 0x0bbf r/w [7:0] 0x0 input selection for srtd_31.b (refer to table 18 for definition) table 18: input selection values value description value description 0x00 0 0x39 2 frame + 2 line + 1 pixel toggle 0x01 1 0x3a hcount[0] 0x02 external tcon input pin 0x3b hcount[1] 0x03 i2c srtd init bit 0x3c vcount[0] 0x04 - 0x1f comp0 - comp27 0x3d vcount[1] 0x20 - 0x37 srtd8 - srtd31 0x3e fcount[0] 0x38 2 frame + 1 line + 2 pixel toggle 0x3f fcount[1] table 17: tcon registers (sheet 7 of 7) register name addr. mode bits default description
55/89 ade3700 pattern generator when the programmed block size is such that the complete 8x8 grid is smaller than the total screen area, the part of the screen area which is outside the 8x8 grid is forced to black. 2.13.2 pattern engine in order to display two patterns simultaneously on the lcd screen, the pattern generator has two pattern display engines. each engine can display horizontal or vertical bicolor stripes, bicolor checkers, color bars, gray scales or color scales. it is also possible to select the video stream from the scaler as a pattern. the pattern engine displays a bi-directional x-y symmetric pattern. two 24-bit colors, c0 and c1, are alternately displayed with a horizontal period of width and vertical period of height. programming a large width and a small height generates horizontal bars whereas the opposite will generate vertical bars. programming small numbers for width and height generates checker patterns. each of the two patterns is also given x and y offset attributes, so that it is possible to center the pattern inside the grid blo cks. a gradient effect can be applied independently on each of the two patterns, to either or both horizontal and vertical directions. the gradient effect takes two parameters: step and delta that define a ramp. 2.13.3 borders the border generator adds a single pixel width border to the whole display area. each of the four sides of the display can be one of 8 independent colors. figure 7: pattern generator (screen split) table 19: pgen registers (sheet 1 of 5) register name addr mode bits default description pgen_pgen_enab 0x0600 [7:1] reserved r/w [0] 0x0 0 = disable pgen block 1 = enable pgen block pgen_grid0 0x0601 r/w [7:0] 0x0 grid row 0 pgen_grid1 0x0602 r/w [7:0] 0x0 grid row 1 pgen_grid2 0x0603 r/w [7:0] 0x0 grid row 2
pattern generator ade3700 56/89 pgen_grid3 0x0604 r/w [7:0] 0x0 grid row 3 pgen_grid4 0x0605 r/w [7:0] 0x0 grid row 4 pgen_grid5 0x0606 r/w [7:0] 0x0 grid row 5 pgen_grid6 0x0607 r/w [7:0] 0x0 grid row 6 pgen_grid7 0x0608 r/w [7:0] 0x0 grid row 7 pgen_grid_x_l 0x0609 r/w [7:0] 0x0 width of a grid block in pixels [7:0] pgen_grid_x_h 0x060a [7:4] reserved r/w [3:0] 0x0 width of a grid block in pixels [11:8] pgen_grid_y_l 0x060b r/w [7:0] 0x0 height of a grid block in pixels [7:0] pgen_grid_y_h 0x060c [7:4] reserved r/w [3:0] 0x0 height of a grid block in pixels [11:8] pgen_grid_x_offset_x_l 0x060d r/w [7:0] 0x0 grid block horizontal offset in pixels [7:0] pgen_grid_x_offset_x_h 0x060e [7:4] reserved r/w [3:0] 0x0 grid block horizontal offset in pixels [11:8] pgen_grid_y_offset_y_l 0x060f r/w [7:4] 0x0 grid block vertical offset in pixels pgen_grid_y_offset_y_h 0x0610 r/w [3:0] pgen_p0_mode 0x0611 r/w pattern 0 control r/w [7:5] 0x0 number of bars in c0 r/w [4:2] 0x0 number of bars in c1 r/w [1] 0x0 0: pattern continues to progress across block boundaries 1: block boundaries cause the pattern to restart r/w [0] 0x0 0: normal mode 1: c0 = video bypass pgen_p1_mode 0x0612 pattern 1 control r/w [7:5] 0x0 number of bars in c0 r/w [4:2] 0x0 number of bars in c1 r/w [1] 0x0 0: pattern continues to progress across block boundaries 1: block boundaries cause the pattern to restart r/w [0] 0x0 0: normal mode 1: c0 = video bypass pgen_p0_width_x_l 0x0613 r/w [7:0] 0x0 pattern 0 bar width [7:0] pgen_p0_width_x_h 0x0614 [7:4] reserved r/w [3:0] 0x0 pattern 0 bar width [11:8] pgen_p0_width_x_offset_l 0x0615 r/w [7:0] 0x0 pattern 0 horizontal offset [7:0] table 19: pgen registers (sheet 2 of 5) register name addr mode bits default description
57/89 ade3700 pattern generator pgen_p0_width_x_offset_h 0x0616 [7:4] reserved r/w [3:0] 0x0 pattern 0 horizontal offset [11:8] pgen_p0_height_y_l 0x0617 r/w [7:0] 0x0 pattern 0 bar height [7:0] pgen_p0_height_y_h 0x0618 r/w [7:4] 0x0 pattern 0 vertical sequence increment r/w [3:0] 0x0 pattern 0 bar height [11:8] pgen_p0_height_y_offset_l 0x0619 r/w [7:0] 0x0 pattern 0 vertical offset [7:0] pgen_p0_height_y_offset_h 0x061a [7:4] reserved r/w [3:0] 0x0 pattern 0 vertical offset [11:8] pgen_p1_width_x_l 0x061b r/w [7:0] 0x0 pattern 1 bar width [7:0] pgen_p1_width_x_h 0x061c [7:4] reserved r/w [3:0] 0x0 pattern 1 bar width [11:8] pgen_p1_width_x_offset_l 0x061d r/w [7:0] 0x0 pattern 1 horizontal offset [7:0] pgen_p1_width_x_offset_h 0x061e [7:4] reserved r/w [3:0] 0x0 pattern 1 horizontal offset [11:8] pgen_p1_height_y_l 0x061f r/w [7:0] 0x0 pattern 1 bar height [7:0] pgen_p1_height_y_h 0x0620 r/w [7:4] 0x0 pattern 1 vertical sequence increment r/w [3:0] 0x0 pattern 1 bar height [11:8] pgen_p1_height_y_offset_l 0x0621 r/w [7:0] 0x0 pattern 1 vertical offset [7:0] pgen_p1_height_y_offset_h 0x0622 [7:4] reserved r/w [3:0] 0x0 pattern 1 vertical offset [11:8] pgen_p0_color_r_c0 0x0623 r/w [7:0] 0x0 pattern 0 color c0 - red pgen_p0_color_g_c0 0x0624 r/w [7:0] 0x0 pattern 0 color c0 - green pgen_p0_color_b_c0 0x0625 r/w [7:0] 0x0 pattern 0 color c0 - blue pgen_p0_color_r_c1 0x0626 r/w [7:0] 0x0 pattern 0 color c1 - red pgen_p0_color_g_c1 0x0627 r/w [7:0] 0x0 pattern 0 color c1 - green pgen_p0_color_b_c1 0x0628 r/w [7:0] 0x0 pattern 0 color c1 - blue pgen_p1_color_r_c0 0x0629 r/w [7:0] 0x0 pattern 1 color c0 - red pgen_p1_color_g_c0 0x062a r/w [7:0] 0x0 pattern 1 color c0 - green pgen_p1_color_b_c0 0x062b r/w [7:0] 0x0 pattern 1 color c0 - blue pgen_p1_color_r_c1 0x062c r/w [7:0] 0x0 pattern 1 color c1 - red pgen_p1_color_g_c1 0x062d r/w [7:0] 0x0 pattern 1 color c1 - green pgen_p1_color_b_c1 0x062e r/w [7:0] 0x0 pattern 1 color c1 - blue pgen_p0_graddelta_r 0x062f r/w [7:0] 0x0 pattern 0 gradient delta on red pgen_p0_graddelta_g 0x0630 r/w [7:0] 0x0 pattern 0 gradient delta on green pgen_p0_graddelta_b 0x0631 r/w [7:0] 0x0 pattern 0 gradient delta on blue table 19: pgen registers (sheet 3 of 5) register name addr mode bits default description
pattern generator ade3700 58/89 pgen_p0_gradstep_x 0x0632 r/w [7:0] 0x0 pattern 0 gradient horizontal step pgen_p0_gradstep_y 0x0633 r/w [7:0] 0x0 pattern 0 gradient vertical step pgen_p1_graddelta_r 0x0634 r/w [7:0] 0x0 pattern 1 gradient delta on red pgen_p1_graddelta_g 0x0635 r/w [7:0] 0x0 pattern 1 gradient delta on green pgen_p1_graddelta_b 0x0636 r/w [7:0] 0x0 pattern 1 gradient delta on blue pgen_p1_gradstep_x 0x0637 r/w [7:0] 0x0 pattern 1 gradient horizontal step pgen_p1_gradstep_y 0x0638 r/w [7:0] 0x0 pattern 1 gradient vertical step pgen_p0_seq_col0_col1 0x0639 [7] reserved r/w [6:4] 0x0 pattern 0 bar 1 color [3] reserved r/w [2:0] 0x0 pattern 0 bar 0 color pgen_p0_seq_col2_col3 0x063a [7] reserved r/w [6:4] 0x0 pattern 0 bar 3 color [3] reserved r/w [2:0] 0x0 pattern 0 bar 2 color pgen_p0_seq_col4_col5 0x063b [7] reserved r/w [6:4] 0x0 pattern 0 bar 5 color [3] reserved r/w [2:0] 0x0 pattern 0 bar 4 color pgen_p0_seq_col6_col7 0x063c [7] reserved r/w [6:4] 0x0 pattern 0 bar 7 color [3] reserved r/w [2:0] 0x0 pattern 0 bar 6 color pgen_p1_seq_col0_col1 0x063d [7] reserved r/w [6:4] 0x0 pattern 1 bar 1 color [3] reserved r/w [2:0] 0x0 pattern 1 bar 0 color pgen_p1_seq_col2_col3 0x063e [7] reserved r/w [6:4] 0x0 pattern 1 bar 3 color [3] reserved r/w [2:0] 0x0 pattern 1 bar 2 color pgen_p1_seq_col4_col5 0x063f [7] reserved r/w [6:4] 0x0 pattern 1 bar 5 color [3] reserved r/w [2:0] 0x0 pattern 1 bar 4 color table 19: pgen registers (sheet 4 of 5) register name addr mode bits default description
59/89 ade3700 pattern generator pgen_p1_seq_col6_col7 0x0640 [7] reserved r/w [6:4] 0x0 pattern 1 bar 7 color [3] reserved r/w [2:0] 0x0 pattern 1 bar 6 color pgen_b_top_bottom 0x0641 r/w [7] 0x0 top border enable r/w [6] 0x0 top border red; 0 = off, 1= on r/w [5] 0x0 top border green; 0 = off, 1= on r/w [4] 0x0 top border blue; 0 = off, 1= on r/w [3] 0x0 bottom border enable r/w [2] 0x0 bottom border red; 0 = off, 1= on r/w [1] 0x0 bottom border green; 0 = off, 1= on r/w [0] 0x0 bottom border blue; 0 = off, 1= on pgen_b_left_right 0x0642 r/w [7] 0x0 left border enable r/w [6] 0x0 left border red; 0 = off, 1= on r/w [5] 0x0 left border green; 0 = off, 1= on r/w [4] 0x0 left border blue; 0 = off, 1= on r/w [3] 0x0 right border enable r/w [2] 0x0 right border red; 0 = off, 1= on r/w [1] 0x0 right border green; 0 = off, 1= on r/w [0] 0x0 right border blue; 0 = off, 1= on pgen_x_total_l 0x0643 r/w [7:0] 0x0 total horizontal size [7:0] pgen_x_total_h 0x0644 [7:4] reserved r/w [3:0] 0x0 total horizontal size [11:8] pgen_y_total_l 0x0645 r/w [7:0] 0x0 total vertical size [7:0] pgen_y_total_h 0x0646 [7:4] reserved r/w [3:0] 0x0 total vertical size [11:8] table 19: pgen registers (sheet 5 of 5) register name addr mode bits default description
srgb ade3700 60/89 2.14 srgb the srgb block performs two primary functions: 1. parametric gamma correction on multiple windows or full screen, used for video enhancement in a window and digital contrast/brightness control. the window coordinates are set by tcon registers. 2. 3d color cube warping rgb color space. 2.14.1 parametric gamma, digital contrast / brightness on multiple windows the function can be applied to the entire window by programming the window control to full screen. each color channel acts independently. simple digital contrast and brightness can be programmed using this hardware function. the desired window coordinates are programmed into the tcon. 2.14.2 color space warp the 8 corners of the color cube are independently controlled in 3d space with smooth interpolation of intermediate colors. registers are 2s complement color deltas. for example, to make white more like red, program srgb_white_r to a small positive value. figure 8: color space warp table 20: srgb registers (sheet 1 of 3) register name addr mode bits default description srgb_ctrl 0x0d00 r/w [7:6] 0x0 reserved r/w [5:4] 0x0 gamma_b control 0x0: disable 0x1: full screen 0x2: windowed 0x3: reserved r/w [3:2] 0x0 gamma_a control 0x0: disable 0x1: full screen 0x2: windowed 0x3: reserved r/w [1:0] 0x0 srgb control 0x0: disabled 0x1: full screen 0x2: windowed 0x3: reserved srgb_black_r 0x0d01 r/w [7:0] 0x0 black point red delta color space warp in out
61/89 ade3700 srgb srgb_black_g 0x0d02 r/w [7:0] 0x0 black point green delta srgb_black_b 0x0d03 r/w [7:0] 0x0 black point blue delta srgb_red_r 0x0d04 r/w [7:0] 0x0 red point red delta srgb_red_g 0x0d05 r/w [7:0] 0x0 red point green delta srgb_red_b 0x0d06 r/w [7:0] 0x0 red point blue delta srgb_green_r 0x0d07 r/w [7:0] 0x0 green point red delta srgb_green_g 0x0d08 r/w [7:0] 0x0 green point green delta srgb_green_b 0x0d09 r/w [7:0] 0x0 green point blue delta srgb_blue_r 0x0d0a r/w [7:0] 0x0 blue point red delta srgb_blue_g 0x0d0b r/w [7:0] 0x0 blue point green delta srgb_blue_b 0x0d0c r/w [7:0] 0x0 blue point blue delta srgb_yellow_r 0x0d0d r/w [7:0] 0x0 yellow point red delta srgb_yellow_g 0x0d0e r/w [7:0] 0x0 yellow point green delta srgb_yellow_b 0x0d0f r/w [7:0] 0x0 yellow point blue delta srgb_cyan_r 0x0d10 r/w [7:0] 0x0 cyan point red delta srgb_cyan_g 0x0d11 r/w [7:0] 0x0 cyan point green delta srgb_cyan_b 0x0d12 r/w [7:0] 0x0 cyan point blue delta srgb_magenta_r 0x0d13 r/w [7:0] 0x0 magenta point red delta srgb_magenta_g 0x0d14 r/w [7:0] 0x0 magenta point green delta srgb_magenta_b 0x0d15 r/w [7:0] 0x0 magenta point blue delta srgb_white_r 0x0d16 r/w [7:0] 0x0 white point red delta srgb_white_g 0x0d17 r/w [7:0] 0x0 white point green delta srgb_white_b 0x0d18 r/w [7:0] 0x0 white point blue delta srgb_gamma_a_red_a 0x0d19 r/w [7:0] 0x0 parametric a gamma a red, gamma srgb_gamma_a_red_b 0x0d1a r/w [7:0] 0x0 parametric a gamma b red, contrast srgb_gamma_a_red_c 0x0d1b r/w [7:0] 0x0 parametric a gamma c red, brightness srgb_gamma_a_green_a 0x0d1c r/w [7:0] 0x0 parametric a gamma a green, gamma srgb_gamma_a_green_b 0x0d1d r/w [7:0] 0x0 parametric a gamma b green, contrast srgb_gamma_a_green_c 0x0d1e r/w [7:0] 0x0 parametric a gamma c green, brightness srgb_gamma_a_blue_a 0x0d1f r/w [7:0] 0x0 parametric a gamma a blue, gamma srgb_gamma_a_blue_b 0x0d20 r/w [7:0] 0x0 parametric a gamma b blue, contrast srgb_gamma_a_blue_c 0x0d21 r/w [7:0] 0x0 parametric a gamma c blue, brightness srgb_gamma_b_red_a 0x0d22 r/w [7:0] 0x0 parametric b gamma a red, gamma srgb_gamma_b_red_b 0x0d23 r/w [7:0] 0x0 parametric gamma b red, contrast srgb_gamma_b_red_c 0x0d24 r/w [7:0] 0x0 parametric gamma c red, brightness table 20: srgb registers (sheet 2 of 3) register name addr mode bits default description
on-screen display (osd) ade3700 62/89 2.15 on-screen display (osd) the integrated on-screen display (osd) controller is a character-based overlay with a high level of features and over 100 kbits of on-board dedicated ram storage. l 15 row by 30 column character-mapped display l four user-definable windows l 12x18-pixel characters with optional horizontal and vertical doubling on a row-by-row basis l two 16-entry 24-bit rgb user-definable color maps l 192 ram-based monochrome 1 bpp characters l 64 ram-based graphics 4 bpp characters l text character attributes: foreground/background color, blinking l graphics character attributes: per-pixel color, vertical/horizontal mirroring l row attributes: double width, double height l window attributes: window visibility, position, size, border shadow, color table l global attributes: osd visibility, osd screen position, alpha fade in/fade out, global size doubling, rotation in ninety-degree increments l single-bit enable/disable for information on osd programming, see the osd programming manual. 2.15.1 osd access via i2c the osd uses a dedicated memory space that is accessed through an i2c port. the data stream sent to the osd register starts with two header bytes. these specify the type of transfer and the row/column position for screen map transfers, the character index for font definition transfers, or the color index for color map transfers. a stream of osd writes to the osd i2c register can fill in a segment of the osd memory space with an internal auto-incrementing index register. the protocol is as follows: 1. issue a start sequence with the r/w bit set to w. 2. write to the osd register. the first byte transferred is the index of the first internal osd register to be written. the next byte contains the data to be written to that register. subsequent bytes are written to successive internal osd registers. 3. continue writing data bytes until the desired range of osd internal registers has been written (the ade3700 device will issue an ack on each transfer). 4. issue an i2c stop sequence. srgb_gamma_b_green_a 0x0d25 r/w [7:0] 0x0 parametric gamma a green, gamma srgb_gamma_b_green_b 0x0d26 r/w [7:0] 0x0 parametric gamma b green, contrast srgb_gamma_b_green_c 0x0d27 r/w [7:0] 0x0 parametric gamma c green, brightness srgb_gamma_b_blue_a 0x0d28 r/w [7:0] 0x0 parametric gamma a blue, gamma srgb_gamma_b_blue_b 0x0d29 r/w [7:0] 0x0 parametric gamma b blue, contrast srgb_gamma_b_blue_c 0x0d2a r/w [7:0] 0x0 parametric gamma c blue, brightness table 20: srgb registers (sheet 3 of 3) register name addr mode bits default description
63/89 ade3700 on-screen display (osd) character display there are two 96-character monochrome fonts and two 32-character four-bit color fon ts, a total of 256 characters. the four bits of color are an index into one of two 16 entry color lookup tables. entries in the color lookup table specify a 24-bit rgb color. all fonts and the color look-up table are ram-based and must be downloaded to the osds internal ram before use. font addressing is as follows: character indexes 0x00-0x1f refer to color font 0, 0x20-0x7f refer to monochrome font 0, 0x80-0x9f refer to color font 1 and 0xa0-0xff refer to monochrome font 1. screen map the osd uses a character map of 15 rows x 30 columns. each character occupies one byte. the value of each byte indicates the character to display. the osd character map is addressed by specifying the row and column as part of the data transfer. attribute map the attribute map is defined as 16 rows by 31 columns. it has an extra row and an extra column compared to the screen map. the values corresponding to printable row/column addresses provide character attributes. each character on the screen has an attribute byte specifying (in the case of monochrome fonts) three bits of background color, four bits of foreground color, and a blink on/off bit. blinking, when enabled, has a period of 100 frames (50 frames on, 50 frames off). column 31 of each row contains row attributes. these include the fourth bit of the background color and two bits controlling double-height and double-width text. row 15 contains global attributes, including vertical and horizontal osd position on the screen, alpha blending, shadow/bordering, osd rotation, color map selection, and normal/double size. alpha blending allows the osd display to be mixed with the incoming video signal for transparency figure 9: character attribute map character attributes r ow a ttribut es 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 wa wa ga ga wa wa = window attributes ga = global attributes
on-screen display (osd) ade3700 64/89 effects. an alpha value of 255 makes the osd opaque, while a value of 0 makes the osd invisible, with a linear ramp of transparency between these two endpoints. separate registers control alpha for foreground and background pixels. a fade-in/fade-out feature ramps the alpha values every six frames, starting from their current value and going up or down the sequence: 0, 16, 32, 64, 128, 192, 224, 240, 255. row 15 also contains definitions for the four display windows. these windows define regions on the screen to which borders and shadows can be applied. (they are not analogous to windows in a gui display, in that they do not represent four independent data displays. there is only one character map. the windows essentially define an area around which a border can be drawn or to which attributes can be assigned.) windows also determine which of the two color tables will be used for the characters inside. windows have a fixed precedence: window 0 has the highest precedence and window 3 the lowest. when windows overlap, the precedence determines which borders will be displayed and which color tables will be used in the overlapping area. monochrome and color fonts are affected differently by attribute bytes. monochrome characters are affected by shadows and borders, and have their color specified by the foreground/background attributes. color characters interpret the attribute byte differently than monochrome characters, using it to define blinking and 90-degree rotations rather than blinking, foreground color, and background color. color tables there are two color tables, each containing sixteen entries by three bytes each, giving a 24-bit rgb value for each entry. entry 0 is used for the shadow color for monochrome characters and borders. color-table selection is made on a window-by-window basis. when writing the color table, the row value in the first header byte is interpreted as the color table index, while the column value in the second header byte encoded to select the color table (0 or 1) and the primary color (red, green, or blue). the data byte following the second header byte is written to the selected (table, index, primary) location. font data font data is sent to the osd through burst transfers. the first header byte selects the transfer type and provides three bits of the character index, while the second header byte selects transfer type c and gives the remaining five bits of offset. the data bytes for the character follow, given from top to bottom and left to right in the character cell. a monochrome character is 27 bytes long, with two scan-lines occupying three bytes. a color character is four times as long as a monochrome character (108 bytes), with each byte containing two four-bit pixels. both color and monochrome fonts are 12 pixels wide and 18 high. transfer formats the transfer format consists of two header bytes and a v ariable number of data bytes. the header bytes determine the type of transfer (character, attribute, monochrome font, color font, or color table). addressing is by row and column in the case of character or attribute transfers, and by character index in the case of font transfers. when writing to the color table, the column field determines the color table and r/g/b selection.
65/89 ade3700 on-screen display (osd) table 21: osd access header definition header byte bits description first [7:4] type of data transfer. valid values are: 0x8: screen map 0x9: color lut 0xa: attribute map 0xc: font data all others: reserved [3:0] for screen map or attribute map access, this is the row index. for color lut access, this is the color index. for font data access, bits [2:0] are the msbs of the character index. second [7:6] type of data burst: 0x0: a/b modes: only one data byte follows this header byte. 0x1: c mode: all bytes following this header byte are data bytes until the serial interface indicates an end-of-transmission. the osd internally auto-increments after each byte. in screen and attribute map access modes the column number is incremented after each byte, wrapping to the beginning of the next row once column 29 is passed and wrapping to row 0 if row 14 is passed. either mode may be used for display and character attribute modes, except for the off-screen attributes in column 15 and row 30, which must use mode a/b. font definition mode must use mode c. [5] must be set to zero [4:0] in screen and attribute map access modes, this is the column number. in font data access mode, this gives the 5 lsbs of the character index. in color lut access mode, it selects the table number and color to be written: 0x0: lut 0, red 0x1: lut 0, green 0x2: lut 0, blue 0x3: lut 1, red 0x4: lut 1, green 0x5: lut 1, blue 0x6 - 0x7: reserved table 22: osd attribute map definition (sheet 1 of 4) row column bits description 15 12 [7:0] vertical osd position / 4 15 13 [7:0] horizontal osd position / 5
on-screen display (osd) ade3700 66/89 15 15 [7] 0: osd off 1: osd on [6:5] 0x0: plain characters 0x1: border characters 0x2: shadow characters 0x3: reserved [4:3] reserved [2] 0: normal 1: flip osd [1] 0: fade off 1: fade on [0] 0: normal size 1: double size 15 19 [7:0] foreground alpha blending 15 20 [7:0] background alpha blending 15 0 [7:4] window 0 row start [3:0] window 0 row end 15 3 [7:4] window 1 row start [3:0] window 1 row end 15 6 [7:4] window 2 row start [3:0] window 2 row end 15 9 [7:4] window 3 row start [3:0] window 3 row end 15 1 [7:3] window 0 column start [2] window 0 visibility 0: off 1: on [1] reserved [0] window 0 shadow enable 15 4 [7:3] window 1 column start [2] window 1 visibility 0: off 1: on [1] reserved [0] window 1 shadow enable table 22: osd attribute map definition (sheet 2 of 4) row column bits description
67/89 ade3700 on-screen display (osd) 15 7 [7:3] window 2 column start [2] window 2 visibility 0: off 1: on [1] reserved [0] window 2 shadow enable 15 10 [7:3] window 3 column start [2] window 3 visibility 0: off 1: on [1] reserved [0] window 3 shadow enable 15 2 [7:3] window 0 column end [2:0] reserved 15 5 [7:3] window 1 column end [2:0] reserved 15 8 [7:3] window 2 column end [2:0] reserved 15 11 [7:3] window 3 column end [2:0] reserved 15 16 [7:6] window 3 shadow width [5:4] window 2 shadow width [3:2] window 1 shadow width [1:0] window 0 shadow width 15 17 [7:6] window 3 shadow height [5:4] window 2 shadow height [3:2] window 1 shadow height [1:0] window 0 shadow height 15 21 [7:4] reserved [3] window 3 color lut select [2] window 2color lut select [1] window 1 color lut select [0] window 0 color lut select table 22: osd attribute map definition (sheet 3 of 4) row column bits description
flicker ade3700 68/89 2.16 flicker the flicker block computes correlations of the image data with potential inversion patterns of the lcd which in turn allows the microcontroller to modify the polarity signal to cancel large areas of flicker. this function is only useful in smartpanel applications. the incoming image is scored against 8 vertical walsh functions. all patterns are considered vertically, while horizontally the pixels are assumed to be alternating rgb components. the scores (0 to 7) are 32-bit unsigned quantities that reflect the correlation of the programmed window area with the 8 walsh functions. the horizontal inversion of the lcd drivers must be programmed into flicker_ctrl0[2:0]. the most common setting is +-+ or -+- (rgb). a calculation is completed after the number of frames programmed into the frame_cnt_max register (0xca03). with each frame the calculation is performed on only a vertical strip. the width of that strip (in pixels) is determined by the value programmed in the hblock_size register (0xca02) with the following relation: strip width = 2 ^ (3 + hblock_size). the free_run/freeze_scores bit (flicker_ctrl0[4]) enables the final calculation to be captured easily by the mcu. the internal flicker calculation continues to run -- only the update of the i2c registers is blocked when this bit is set to prevent corruption during readout. 0 to 14 30 [7:3] reserved [2] msb of background color for the row [1] double high enable for the row [0] double wide enable for the row 0 to 14 0 to 29 [7:5] 3 lsbs of background color for 1bpp chars no function for 4bpp color chars [4] blink enable [3:0] foreground color for 1bpp chars for 4bpp color chars [3:2]: reserved [1]: flip vertical [0]: flip horizontal table 23: osd register register name addr mode bits default (hex) description osd_port 0x0c02 r/w [7:0] 0 osd access port table 22: osd attribute map definition (sheet 4 of 4) row column bits description
69/89 ade3700 flicker refer to the flicker programming guide for more details. table 24: flicker registers (sheet 1 of 2) register name addr mode bits default description flk_ctrl 0x0ca1 r/w [7:6] 0x0 reserved r/w [5] 0x1 0: straight line uniform function 1: straight line hill function (normal) r/w [4] 0x0 0: free-running 1: freeze scores set to a 1 when the microcontroller is reading multibyte scores to prevent update corruption. r/w [2:0] 0x5 horizontal subpixel polarity inversion pattern of lcd (even/odd pixels) 0x0: -r-g-b / +r+g+b 0x1: -r-g+b / +r+g-b 0x2: -r+g-b / +r-g+b (default) 0x3: -r+g+b / +r-g-b 0x4: +r-g-b / -r+g+b 0x5: +r-g+b / -r+g-b 0x6: +r+g-b / -r-g+b 0x7: +r+g+b / -r-g-b flk_hblock_size 0x0ca2 r/w [7:4] [3:0] 0x0 reserved width in pixels of the per frame scored area = 2 ^ (3+ hblock_size) flk_frame_cnt_max 0x0ca3 r/w [7:0] 0x8 number of frames to complete one measurement total number of pixels in a line is: frame_cnt_max * (2 ^ (3+hblock_size)) example: hblock_size = 4; frame_cnt_max = 8; in each frame only one portion of the image is being scored. the width of that portion is 2 ^ (3 + hblock_size) = 128 pixels and the height is the full height of the image. thus the total scored area after 8 frames is 128*8 = 1024 pixels wide. flk_meas0_0 0x0cb1 r/w [7:0] 0x0 score for pattern 0 flk_meas0_1 0x0cb2 r/w [7:0] flk_meas0_2 0x0cb3 r/w [7:0] flk_meas0_3 0x0cb4 r/w [7:0] flk_meas1_0 0x0cb5 r/w [7:0] 0x0 score for pattern 1 flk_meas1_1 0x0cb6 r/w [7:0] flk_meas1_2 0x0cb7 r/w [7:0] flk_meas1_3 0x0cb8 r/w [7:0] flk_meas2_0 0x0cb9 r/w [7:0] 00x score for pattern 2 flk_meas2_1 0x0cba r/w [7:0] flk_meas2_2 0x0cbb r/w [7:0]
gamma ade3700 70/89 2.17 gamma the gamma block performs an 8-bit to 10-bit lookup table on the 3 x 8 bits (r, g, b) color data coming from the lcd scaler. the lookup table (lut ram) contains the corresponding 10-bit output corrected color for each 8-bit input color. the rams are individually programmable (read and write) using i2c access. the memory map is as follows: i2c address 0x1000 to 0x11ff: red ram i2c address 0x1200 to 0x13ff: green ram i2c address 0x1400 to 0x15ff: blue ram even addresses are the 8-bit lsbs of the 10-bit gamma value. odd addresses are the 2 msbs. flk_meas2_3 0x0cbc r/w [7:0] flk_meas3_0 0x0cbd r/w [7:0] 0x0 score for pattern 3 flk_meas3_1 0x0cbe r/w [7:0] flk_meas3_2 0x0cbf r/w [7:0] flk_meas3_3 0x0cc0 r/w [7:0] flk_meas4_0 0x0cc1 r/w [7:0] 0x0 score for pattern 4 flk_meas4_1 0x0cc2 r/w [7:0] flk_meas4_2 0x0cc3 r/w [7:0] flk_meas4_3 0x0cc4 r/w [7:0] flk_meas5_0 0x0cc5 r/w [7:0] 0x0 score for pattern 5 flk_meas5_1 0x0cc6 r/w [7:0] flk_meas5_2 0x0cc7 r/w [7:0] flk_meas5_3 0x0cc8 r/w [7:0] flk_meas6_1 0x0cc9 r/w [7:0] 0x0 score for pattern 6 flk_meas6_2 0x0cca r/w [7:0] flk_meas6_3 0x0ccb r/w [7:0] flk_meas6_4 0x0ccc r/w [7:0] flk_meas7_0 0x0ccd r/w [7:0] 0x0 score for pattern 7 flk_meas7_1 0x0cce r/w [7:0] flk_meas7_2 0x0ccf r/w [7:0] flk_meas7_3 0x0cd0 r/w [7:0] table 24: flicker registers (sheet 2 of 2) register name addr mode bits default description
71/89 ade3700 apc 2.18 apc apc (formerly known as arithmos perfect color) dithers an input 10 bit video stream down to 4-8 output bits. the dithering is done in space and time in such a way that the eye does not perceive objectionable artifacts such as: l fixed dither patterns l contours l flickering pixels l phase correlated flickering, which creates wave patterns known as swimming table 25: gamma registers register name addr mode bits default description gamma_ctrl 0x0c10 r/w [7:4] 0x0 reserved [3] 0x0 0: normal 1: disable ram access [2] 0x0 0: normal 1: test mode [1:0] 0x0 gamma mode select 0x0: 10-bit linear bypass 0x1: 8-bit->10-bit gamma table (normal) 0x2: 8-bit linear bypass (no interpolation) 0x3: 8-bit->10-bit gamma table (normal) table 26: apc registers register name addr mode bits default description apc_apc0 0x0c20 [7] reserved r/w [6:5] 0x0 frame modulation period - 1 r/w [4:1] 0x0 0x0 - 0x3: 8-bit out 0x4: 4b out 0x5: 5b out 0x6: 6b out 0x7: 7b out 0x8: 8-bit out r/w [0] 0x0 0: normal 1: disable apc -- truncate lsbs apc_apc1 0x0c21 [7:2] reserved r/w [1] 0x0 offset the phase lut r/w [0] 0x0 offset the dither lut
output multiplexer ade3700 72/89 2.19 output multiplexer the output multiplexer formats the single wide data stream from the output of the apc block into a single or double wide data path for the flat panel. the architecture is shown in figure 10 . latency is not important, as long as the timing relationship between hsync, vsync, enab and data is preserved at the output. in double wide mode, the first pixel must be properly aligned even if the number of pixels in blanking or active are odd. the divide-by-2 circuit can be set to resync per line (based on data_enab and hsync_in edge) and per frame (based on vsync_in edge). the most reliable timing is when hsync and vsync are in the low counts of the timing core counters (i.e. hsync_set and hsync_rst are both below the active data region start/end counts). in the event that hsync and vsync are in the high (after active region) counts, the device should be set to sync to data_enab_re. the per pin delay and rsds logic occur after the last latch and are implemented on all channels to maintain delay balance between signals that go into rsds mode (data and clk/hsync) and those that do not (de/vsync and tcon). figure 10: output mux block diagram right shift byte flip red & blue swap right shift byte flip right shift byte flip rin[7:0] 8 gin[7:0] 8 bin[7:0] 8 8 8 8 8 8 8 single to double wide converter flops 24 48 data inversion rsds logic and per pin delay flops output mux/reg rda[7:0] gda[7:0] bda[7:0] rdb[7:0] gdb[7:0] bdb[7:0] 48 2 inv_a inv_b hclk enab_in hsync_in vsync_in tcon_in[13:0] pwm_a_in pwm_b_in 2 14 tci[13:0] tcon_out[7:0] routa[7:0] gouta[7:0] bouta[7:0] routb[7:0] goutb[7:0] boutb[7:0] enab_out hsync_out vsync_out clk_out 8 48 3
73/89 ade3700 output multiplexer 2.19.1 sub block function 2.19.1.1 right shift l shifts right from 0 to 4 positions, f ills from the top with zeroes l out_mux_ctrl1[2:0] 2.19.1.2 byte flip l flips data bits in a byte from lsb to msb, i.e. out[7:0] = in[0:7] l out_mux_ctrl0[4] 2.19.1.3 red & blue swap l swaps red and blue channels, i.e. out[23:0] = {in[7:0],in[15:8],in[23:16]} l out_mux_ctrl0[3] 2.19.1.4 single to double wide converter l in single wide mode (out_mux_ctrl0[1] = 0) flops all data into either a or b channels depending on out_mux_ctrl0[2] either inv_a or inv_b is active depending on active channel l in double wide mode (out_mux_ctrl0[1] = 1) flops data into a/b or b/a positions depending on out_mux_ctrl0[2]. divides clock by 2 (hclk = half speed dclk), resyncing each line with data enable output data transitions as posedge/negedge as set in out_mux_ctrl0[5] can handle odd output htotal (i.e. all divide by 2s and state machines must be resynced per line) 2.19.1.5 data inversion l resyncs at the end of each line to inactive state with data enable falling edge - l invert is possible on the first pixel C compares 1 st pixel to blanking value l compares subsequent 24-bit/48-bit data to the last output; if more bits flip (i.e. hamming distance > active_bit_width/2), invert data word and toggle invert pin l counts only active bits in hamming distance as determined by right shift and bit flip settings; zeroes out non active data signals at output l controls: out_mux_ctrl1[4] - a and b channels have separate independent - a and b channels treated as one 48-bit channel, inv_a = inv_b out_mux_ctrl1[5] - data invert output polarity out_mux_ctrl1[6] - data invert enable l data invert pins can also be driven by tcon srtd[26] and srtd[27] for panel balancing (out_mux_ctrl2[6] and out_mux_ctrl2[7]) l data can be inverted at the front end of the data inversion detection using tcon signals, either separate or combined channels (out_mux_ctrl3[0]) 2.19.1.6 output mux / reg l combines all signals to form the desired outputs
output multiplexer ade3700 74/89 l last point the data is flopped with dclk before the pins l gated clock available from tcon_srtd[12] in tcon mode l see tables 2.2 - 2.5 for configurations. table 27: output mux specification (sheet 1 of 2) enable data out_mux_ctrl0[0] 0011111111 1 enable tcon out_mux_ctrl1[3]00xx111111 1 ab or ba out_mux_ctrl0[2] x x 0 1 x x 0 1 x x x double out_mux_ctrl0[1]xx00110011 1 right shiftout_mux_ctrl1[2:0]xxxx>0>0xx0>0>0 byte flipout_mux_ctrl0[4]xxxx0 1xxx0 1 pwm enable out_mux_ctrl3[1] 0111110000 0 pwm mux mode out_mux_ctrl3[2]x11111xxxxx oba7 0 0 bda7 bda7 pwma bda7 bda7 bda7 bda7 bda7 bda7 oba6 0 0 bda6 bda6 bda6 bda6 bda6 bda6 bda6 bda6 bda6 oba5 0 0 bda5 bda5 bda5 bda5 bda5 bda5 bda5 bda5 bda5 oba4 0 0 bda4 bda4 bda4 bda4 bda4 bda4 bda4 bda4 bda4 oba3 0 0 bda3 bda3 bda3 bda3 bda3 bda3 bda3 bda3 bda3 oba2 0 0 bda2 bda2 bda2 bda2 bda2 bda2 bda2 bda2 bda2 oba1 0 0 bda1 bda1 bda1 bda1 bda1 bda1 bda1 bda1 bda1 oba0 0 0 bda0 bda0 bda0 pwma bda0 bda0 bda0 bda0 bda0 oga7 0 0 gda7 gda7 pwmb gda7 gda7 gda7 gda7 gda7 gda7 oga6 0 0 gda6 gda6 gda6 gda6 gda6 gda6 gda6 gda6 gda6 oga5 0 0 gda5 gda5 gda5 gda5 gda5 gda5 gda5 gda5 gda5 oga4 0 0 gda4 gda4 gda4 gda4 gda4 gda4 gda4 gda4 gda4 oga3 0 0 gda3 gda3 gda3 gda3 gda3 gda3 gda3 gda3 gda3 oga2 0 0 gda2 gda2 gda2 gda2 gda2 gda2 gda2 gda2 gda2 oga1 0 0 gda1 gda1 gda1 gda1 gda1 gda1 gda1 gda1 gda1 oga0 0 0 gda0 gda0 gda0 pwmb gda0 gda0 gda0 gda0 gda0 ora7 0 0 rda7 rda7 rda7 rda7 rda7 rda7 rda7 tci11 rda7 ora6 0 0 rda6 rda6 rda6 rda6 rda6 rda6 rda6 rda6 rda6 ora5 0 0 rda5 rda5 rda5 rda5 rda5 rda5 rda5 rda5 rda5 ora4 0 0 rda4 rda4 rda4 rda4 rda4 rda4 rda4 rda4 rda4 ora3 0 0 rda3 rda3 rda3 rda3 rda3 tci11 rda3 rda3 rda3 ora2 0 0 rda2 rda2 rda2 rda2 rda2 tci10 rda2 rda2 rda2 ora1 0 0 rda1 pwma rda1 rda1 rda1 tci9 rda1 rda1 rda1
75/89 ade3700 output multiplexer tci13 = tcon_in13, orb7 = output red b channel bit 7, rda3 = red a channel bit 3, etc. pwma = pwm_a input. ora0 0 0 rda0 pwmb rda0 rda0 rda0 tci8 rda0 rda0 tci11 obb7 0 0 pwma bdb7 bdb7 bdb7 bdb7 bdb7 bdb7 tci10 bdb7 obb6 0 0 pwmb bdb6 bdb6 bdb6 bdb6 bdb6 bdb6 bdb6 bdb6 obb5 0 0 bdb5 bdb5 bdb5 bdb5 bdb5 bdb5 bdb5 bdb5 bdb5 obb4 0 0 bdb4 bdb4 bdb4 bdb4 bdb4 bdb4 bdb4 bdb4 bdb4 obb3 0 0 bdb3 bdb3 bdb3 bdb3 bdb3 bdb3 bdb3 bdb3 bdb3 obb2 0 0 bdb2 bdb2 bdb2 bdb2 bdb2 bdb2 bdb2 bdb2 bdb2 obb1 0 0 bdb1 bdb1 bdb1 bdb1 bdb1 bdb1 bdb1 bdb1 bdb1 obb0 0 0 bdb0 bdb0 bdb0 bdb0 bdb0 bdb0 bdb0 bdb0 tci10 ogb7 0 0 gdb7 gdb7 gdb7 gdb7 gdb7 gdb7 gdb7 tci9 gdb7 ogb6 0 0 gdb6 gdb6 gdb6 gdb6 gdb6 gdb6 gdb6 gdb6 gdb6 ogb5 0 0 gdb5 gdb5 gdb5 gdb5 gdb5 gdb5 gdb5 gdb5 gdb5 ogb4 0 0 gdb4 gdb4 gdb4 gdb4 gdb4 gdb4 gdb4 gdb4 gdb4 ogb3 0 0 gdb3 gdb3 gdb3 gdb3 gdb3 gdb3 gdb3 gdb3 gdb3 ogb2 0 0 gdb2 gdb2 gdb2 gdb2 gdb2 gdb2 gdb2 gdb2 gdb2 ogb1 0 0 gdb1 gdb1 gdb1 gdb1 gdb1 gdb1 gdb1 gdb1 gdb1 ogb0 0 0 gdb0 gdb0 gdb0 gdb0 gdb0 gdb0 gdb0 gdb0 tci9 orb7 0 0 rdb7 rdb7 rdb7 rdb7 rdb7 rdb7 rdb7 tci8 rdb7 orb6 0 0 rdb6 rdb6 rdb6 rdb6 rdb6 rdb6 rdb6 rdb6 rdb6 orb5 0 0 rdb5 rdb5 rdb5 rdb5 rdb5 rdb5 rdb5 rdb5 rdb5 orb4 0 0 rdb4 rdb4 rdb4 rdb4 rdb4 rdb4 rdb4 rdb4 rdb4 orb3 0 0 rdb3 rdb3 rdb3 rdb3 tci11 rdb3 rdb3 rdb3 rdb3 orb2 0 0 rdb2 rdb2 rdb2 rdb2 tci10 rdb2 rdb2 rdb2 rdb2 orb1 0 0 rdb1 rdb1 rdb1 rdb1 tci9 rdb1 rdb1 rdb1 rdb1 orb0 0 0 rdb0 rdb0 rdb0 rdb0 tci8 rdb0 rdb0 rdb0 tci8 table 28: clk_out mux specification enable data out_mux_ctrl0[0] 01111 double out_mux_ctrl0[1] x0011 clk invert out_mux_ctrl0[5] x0101 clk_out 0 dotclk !dotclk hclk !hclk table 27: output mux specification (sheet 2 of 2)
output multiplexer ade3700 76/89 eni = enab_in, hsi = hsync_in, vsi = vsync_in. 2.19.2 rsds in rsds mode, clk and hsync outputs are the differential clock pair. all 48 data ports are combined into neighboring pairs (e.g. orb0 and orb1 are differential pairs in rsds mode). the lower index is the positive sense differential output. tcon, data_enab and vsync outputs are unchanged. data_enab and vsync can be used to output lvcmos data inversion signals independent of rsds mode. the following table indicates the pin, timing and data relationships in rsds mode. table 29: sync mux specification enable data out_mux_ctrl0[0] 0 1 1 enable tcon out_mux_ctrl1[3] 0 0 1 enab_out 0 eni inv_a hsync_out 0 hsi tci_gated_clk vsync_out 0 vsi inv_b table 30: tcon mux specification enable tcon out_mux_ctrl1[3] x x 0 enable pwm out_mux_ctrl3[1] 0 1 1 pwm mux mode out_mux_ctrl3[2] x 0 1 tcon_out7 tci7 tci7 tci7 tcon_out6 tci6 tci6 tci6 tcon_out5 tci5 tci5 tci5 tcon_out4 tci4 tci4 tci4 tcon_out3 tci3 tci3 tci3 tcon_out2 tci2 tci2 tci2 tcon_out1 tci1 pwm_a tci1 tcon_out0 tci0 pwm_b tci0 table 31: rsds mode specifications rsds time clk_o hsync_o o[r,g,b][a,b](2n) o[r,g,b][a,b](2n+1) t 0 1 bit from 2n !bit from 2n t+1 1 0 bit from 2n+1 !bit from 2n+1
77/89 ade3700 output multiplexer note: hsync_o is the positive clock signal according to the rsds definition. 2.19.3 per pin delay each of the 60 outputs has a per pin programmable delay. the delay is calibrated on the fly to the xclk period, which is assumed to be 37ns. each pin can be delayed by up to 6ns in 0.4ns increments. code 0x0 is the least delay, code 0xf is the maximum delay. the setting is accurate to 0.8ns across pvt. the calibration and resetting is done once per frame after the falling edge of vertical enable to prevent glitches from delay mux changes in the active data period. the delays are active in rsds and normal output modes if enabled in the out_mux_ctrl2 register. t+2 0 1 bit from 2n !bit from 2n t+3 1 0 bit from 2n+1 !bit from 2n+1 table 32: output mux registers (sheet 1 of 4) register name addr mode bits default description omux_ctrl_0 0x0c30 r/w [7] 0x0 in 2 ppc, 0: data invert for a+b comb. 1: data invert a/b separate r/w [6:4] 0x0 0x0 - 0x4: right shift per 8-bit r/g/b 0x5 - 0x7: reserved r/w [3] 0x0 0: normal 1: flip msbs to lsbs r/w [2] 0x0 0: normal 1: swap r and b data r/w [1] 0x0 0: in 1 ppc, a channel active 0: in 2 ppc, left on a, right on b 1: in 1 ppc, b channel active 1: 2ppc, left on b, right on a r/w [0] 0x0 0: single wide, one pix/clk (ppc) 1: double wide, two pix/clk omux_ctrl_1 0x0c31 r/w [7] 0x0 vsync output polarity r/w [6] 0x0 hsync output polarity r/w [5] 0x0 data enable output polarity r/w [4] 0x0 clock output invert r/w [3] 0x0 data invert output polarity r/w [2] 0x0 data invert enable r/w [1] 0x0 0: tcon outputs set to zero 1: tcon outputs active r/w [0] 0x0 0: all data outputs set to zero 1: output enabled table 31: rsds mode specifications (continued) rsds time clk_o hsync_o o[r,g,b][a,b](2n) o[r,g,b][a,b](2n+1)
output multiplexer ade3700 78/89 omux_ctrl_2 0x0c32 r/w [7] 0x0 separate tcon driven invert enable r/w [6] 0x0 tcon driven invert pin enable r/w [5] 0x0 rsds enable r/w [4] 0x0 per pin delay enable r/w [3] 0x0 resync on vsync falling edge r/w [2] 0x0 resync on vsync rising edge r/w [1] 0x0 resync on hsync falling edge r/w [0] 0x0 resync on hsync rising edge omux_dly_ba0 0x0c50 r/w [7:4] 0x0 delay for oba1 r/w [3:0] 0x0 delay for oba0 omux_ dly_ba2 0x0c4f r/w [7:4] 0x0 delay for oba3 r/w [3:0] 0x0 delay for oba2 omux_ dly_ba4 0x0c4e r/w [7:4] 0x0 delay for oba5 r/w [3:0] 0x0 delay for oba4 omux_ dly_ba6 0x0c4d r/w [7:4] 0x0 delay for oba7 r/w [3:0] 0x0 delay for oba6 omux_ dly_ga0 0x0c4c r/w [7:4] 0x0 delay for oga1 r/w [3:0] 0x0 delay for oga0 omux_ dly_ga2 0x0c4b r/w [7:4] 0x0 delay for oga3 r/w [3:0] 0x0 delay for oga2 omux_ dly_ga4 0x0c4a r/w [7:4] 0x0 delay for oga5 r/w [3:0] 0x0 delay for oga4 omux_ dly_ga6 0x0c49 r/w [7:4] 0x0 delay for oga7 r/w [3:0] 0x0 delay for oga6 omux_ dly_ra0 0x0c48 r/w [7:4] 0x0 delay for ora1 r/w [3:0] 0x0 delay for ora0 omux_ dly_ra2 0x0c47 r/w [7:4] 0x0 delay for ora3 r/w [3:0] 0x0 delay for ora2 omux_ dly_ra4 0x0c46 r/w [7:4] 0x0 delay for ora5 r/w [3:0] 0x0 delay for ora4 omux_ dly_ra6 0x0c45 r/w [7:4] 0x0 delay for ora7 r/w [3:0] 0x0 delay for ora6 omux_ dly_bb0 0x0c44 r/w [7:4] 0x0 delay for obb1 r/w [3:0] 0x0 delay for obb0 table 32: output mux registers (sheet 2 of 4) register name addr mode bits default description
79/89 ade3700 output multiplexer omux_ dly_bb2 0x0c43 r/w [7:4] 0x0 delay for obb3 r/w [3:0] 0x0 delay for obb2 omux_ dly_bb4 0x0c42 r/w [7:4] 0x0 delay for obb5 r/w [3:0] 0x0 delay for obb4 omux_ dly_bb6 0x0c41 r/w [7:4] 0x0 delay for obb7 r/w [3:0] 0x0 delay for obb6 omux_ dly_gb0 0x0c40 r/w [7:4] 0x0 delay for orb1 r/w [3:0] 0x0 delay for orb0 omux_ dly_gb2 0x0c3f r/w [7:4] 0x0 delay for orb3 r/w [3:0] 0x0 delay for orb2 omux_ dly_gb4 0x0c3e r/w [7:4] 0x0 delay for orb5 r/w [3:0] 0x0 delay for orb4 omux_ dly_gb6 0x0c3d r/w [7:4] 0x0 delay for orb7 r/w [3:0] 0x0 delay for orb6 omux_ dly_rb0 0x0c3c r/w [7:4] 0x0 delay for orb1 r/w [3:0] 0x0 delay for orb0 omux_ dly_rb2 0x0c3b r/w [7:4] 0x0 delay for orb3 r/w [3:0] 0x0 delay for orb2 omux_ dly_r_b4 0x0c3a r/w [7:4] 0x0 delay for orb5 r/w [3:0] 0x0 delay for orb4 omux_ dly_r_b6 0x0c39 r/w [7:4] 0x0 delay for orb7 r/w [3:0] 0x0 delay for orb6 omux_ dly_tcon_0 0x0c38 r/w [7:4] 0x0 delay for tcon1 r/w [3:0] 0x0 delay for tcon0 omux_ dly_tcon_2 0x0c37 r/w [7:4] 0x0 delay for tcon3 r/w [3:0] 0x0 delay for tcon2 omux_ dly_tcon_4 0x0c36 r/w [7:4] 0x0 delay for tcon5 r/w [3:0] 0x0 delay for tcon4 omux_ dly_tcon_6 0x0c35 r/w [7:4] 0x0 delay for tcon7 r/w [3:0] 0x0 delay for tcon6 omux_ dly_vs_enab 0x0c34 r/w [7:4] 0x0 delay for vsync r/w [3:0] 0x0 delay for enab omux_ dly_clk_hs 0x0c33 r/w [7:4] 0x0 delay for clk r/w [3:0] 0x0 delay for hsync table 32: output mux registers (sheet 3 of 4) register name addr mode bits default description
pulse width modulation (pwm) ade3700 80/89 2.20 pulse width modulation (pwm) the pwm block generates two signals that can be used to control backlight inverter switching power components directly. it is derived from xclk and can be powered up independently of the dotclk and inclk domains. the frequency, duty cycle, polarity and overlap/non-overlap are programmable. the output frequency can be free-running or locked to the output vsync signal. omux_ctrl_3 0x0c51 r/w [7:3] reserved r/w [2] 0x0 pwm mux mode r/w [1] 0x0 pwm enable r/w [0] 0x0 tcon data invert enable, with computed data invert pin. omux_refcount 0x0c52 [7:6] reserved r [5:0] 0x0 returns a value that indicates the ade gate speed -- a function of temp and voltage higher = faster logic table 33: pwm registers (sheet 1 of 2) register name addr mode bits default description pwm_ctrl0 0x01a0 r [7] 0x0 pwm status 0: unlocked 1: locked r/w [6] 0x0 0: lock to cycles_per_frame from the free-running state machine 1: lock to cycles_per_frame register setting r/w [5] 0x0 pwm_a polarity 0: active low 1: active high r/w [4] 0x0 pwm_b polarity 0: active low 1: active high r/w [3] 0x0 0: normal operation 1: force pwm outputs to polarity settings r/w [2] 0x0 0: change period or duty cycle at the end of the current cycle 1: smooth change, period or duty cycle increment/decrement every pwm_step_delay cycle r/w [1] 0x0 0: free-running 1: lock to out_vsync r/w [0] 0x0 0: disable pwm output 1: enable pwm output table 32: output mux registers (sheet 4 of 4) register name addr mode bits default description
81/89 ade3700 dft block 2.21 dft block pwm_ctrl1 0x01a1 r/w [7:4] 0x0 lock 2 nd order gain (power of 2) 0x0 = max 0x3 = typical 0xf = min. r/w [3:0] 0x0 lock gain (power of 2) 0x0 = max 0x6 = typical 0xf = min. pwm_period_l 0x01a2 r/w [7:0] 0x0 period-2 in free-running mode, in xclks pwm_period_h 0x01a3 r/w [7:0] pwm_duty_l 0x01a4 r/w [7:0] 0x0 duty cycle of pwm in xclks pwm_duty_h 0x01a5 r/w [7:0] pwm_overlap_l 0x01a6 r/w [7:0] 0x0 non-overlap of pwms in xclks pwm_overlap_h 0x01a7 r/w [7:0] pwm_step_delay 0x01a8 r/w [7:0] 0x0 in smooth change mode, the number of cycles skipped before the period/duty registers are incremented/decremented pwm_cycles_per_frame_l 0x01a9 r/w [7:0] 0x0 the number of cycles per frame in frame lock mode when not using the internally generated cycles per frame from a previous free-running mode pwm_cycles_per_frame_h 0x01aa r/w [7:0] table 34: dft registers (sheet 1 of 3) register name addr mode bits default description dft_test_mode 0x0f00 [7:4] reserved r/w [3] 0x0 trigger video bus mfsr r/w [2] 0x0 enable output pin mfsr r/w [1] 0x0 clear output pin mfsr r/w [0] 0x0 output pin test override dft_mux_out_mode 0x0f01 [7:6] reserved r/w [5:0] 0x0 mux selector for output porta/b and syncs dft_flop_out_mode 0x0f02 [7:6] reserved r/w [5:0] 0x0 mux selector for synchronous digital debug bus dft_clk_0ut_mode 0x0f03 r/w [7:6] 0x0 divide-by selector for clocks to oclk pin fout = selected clock / (2 ^ value) r/w [5:0] 0x0 mux selector for clocks to oclk pin dft_clk_1_mode 0x0f04 r/w [7:6] 0x0 divide-by selector for clocks to clkout pin fout = selected clock / (2 ^ value) table 33: pwm registers (sheet 2 of 2) register name addr mode bits default description
dft block ade3700 82/89 dft_clk_2_mode 0x0f05 r/w [5:0] 0x0 mux selector for clocks to clkout pin dft_out_disab_0 0x0f06 r/w [7:0] 0x0 disable port a red output in test mode dft_out_disab_1 0x0f07 r/w [7:0] 0x0 disable port a green output in test mode dft_out_disab_2 0x0f08 r/w [7:0] 0x0 disable port a blue output in test mode dft_out_disab_3 0x0f09 r/w [7:0] 0x0 disable port b red output in test mode dft_out_disab_4 0x0f0a r/w [7:0] 0x0 disable port b green output in test mode dft_out_disab_5 0x0f0b r/w [7:0] 0x0 disable port b blue output in test mode dft_out_disab_6 0x0f0c r/w [7:3] 0x0 disable tcon bits [4:0] in test mode r/w [2] 0x0 disable vert sync output in test mode r/w [1] 0x0 disable data enab output in test mode r/w [0] 0x0 disable horz sync output in test mode dft_out_disab_7 0x0f0d [7:5] reserved r/w [4] 0x0 disable clkout output in test mode r/w [3] 0x0 disable oclk output in test mode r/w [2:0] 0x0 disable tcon bits [7:5] in test mode dft_stim_ctrl 0x0f0e [7:6] reserved r/w [0] 0x0 internal stimulus bus enable dft_stim_en_0 0x0f0f r/w [7] 0x0 scl test stimulus enable r/w [6:2] reserved r/w [1] 0x0 adc test stimulus enable r/w [0] 0x0 nc dft_stim_en_1 0x0f10 [7:6] reserved r/w [5] 0x0 tcon test bypass r/w [4] 0x0 omux test stimulus enable r/w [3] 0x0 apc test stimulus enable r/w [2] 0x0 osd test stimulus enable r/w [1] 0x0 scl bypass r/w [0] 0x0 pgen test stimulus enable dft_bist_status 0x0f11 [7:6] reserved r [5] gamma ram bist end r [4] osd cs ram bist end r [3] osd drb ram bist r [2] osd mb ram bist end r [1] scl coeff. ram bist end r [0] scl line buffer ram bist end table 34: dft registers (sheet 2 of 3) register name addr mode bits default description
83/89 ade3700 i2c ram addresses 2.22 i2c ram addresses dft_bist_result_0 0x0f12 [7:6] reserved r [5] scl coeff ram 2 bist fail r [4] scl coeff ram 1 bist fail r [3] scl line buffer 4 bist fail r [2] scl line buffer 3 bist fail r [1] scl line buffer 2 bist fail r [0] scl line buffer 1 bist fail dft_bist_result_1 0x0f13 [7] reserved r [6] gamma blue ram bist fail r [5] gamma green ram bist fail r [4] gamma red ram bist fail r [3] osd cs ram1 bist fail r [2] osd cs ram 2 bist fail r [1] osd drb ram bist fail r [0] osd mb ram bist fail dft_mfsr_done 0x0f14 [7:1] reserved r [0] done signal dft_mfsr_sig_0 0x0f15 r [7:0] 0x0 video bus mfsr dft_mfsr_sig_1 0x0f16 r [7:0] dft_mfsr_sig_2 0x0f17 r [7:0] dft_mfsr_sig_3 0x0f18 r [7:0] table 35: i2c ram addresses name start addr end addr description gam_red 0x1000 11ff gamma lut, red, lsb0,msb0,lsb1,... (256x10) gam_green 0x1200 13ff gamma lut, green, (256x10) gam_blue 0x1400 15ff gamma lut, blue, (256x10) osd_mb 0x1700 175f osd color luts (32x24) osd_cs 0x3000 5f3f osd character map (1344x36x2 copies) osd_drb 0x6000 647f osd screen map (1152x8) scl_coeff 0x9000 98ff scaler coefficient ram (256x36x2 copies) scl_line1 0x9900 a7ff scaler line buffer 1 (1280x24) scl_line2 0xa800 b6ff scaler line buffer 2 (1280x24) scl_line3 0xb700 c5ff scaler line buffer 3 (1280x24) scl_line4 0xc600 d4ff scaler line buffer 4 (1280x24) table 34: dft registers (sheet 3 of 3) register name addr mode bits default description
absolute maximum ratings ade3700 84/89 3 electrical specifications 3.1 absolute maximum ratings 3.2 power consumption matrices * measured at nominal voltage supplies ** measured at +10% voltage supplies * measured at nominal voltage supplies ** measured at +10% voltage supplies symbol parameter min. typ. max. unit avdd18 dvdd18 xvdd18 lvdd18 supply voltage 1.95 v avdd33 dvdd33 supply voltage 3.6 v vin max voltage on 5 volt tolerant input pins 6.1 v t stg storage temperature -40 +150 c table 36: ade3700x symbol parameter min typ* max** unit supply current (analog input, xga@75hz, 78.75mhz) i avdd18 1.8v analog supply (i avdd18 ) 195 203 ma i dvdd18 1.8v digital supply (i dvdd18 ) 228 257 ma i avdd33 3.3v analog supply ( iavdd33 ) 102 105 ma i dvdd33 3.3v digital supply (i dvdd33 ) 4451ma p totana total power consumption (analog input, xga@75hz, 78.75mhz) 1.25 1.48 w table 37: ade3700xs symbol parameter min typ* max** unit supply current (analog input, xga@75hz, 135mhz) i avdd18 1.8v analog supply (i avdd18 ) 200 207 ma i dvdd18 1.8v digital supply (i dvdd18 ) 351 401 ma i avdd33 3.3v analog supply ( iavdd33 ) 104 108 ma i dvdd33 3.3v digital supply (i dvdd33 ) 6880ma p totana total power consumption (analog input, xga@75hz, 135mhz) 1.56 1.89 w
85/89 ade3700 nominal operating conditions 3.3 nominal operating conditions 3.4 preliminary thermal data 3.5 preliminary dc specifications test conditions: dvdd33 = avdd33 = 3.3v, dvdd18 = avdd18 = xvdd18 = lvdd18 = 1.8v and t amb = 25c 3.5.1 lvttl 5 volt tolerant inputs with hysteresis yuv[0:7], yuvclk, hsync, vsync, csync, tcon_in, scl, resetn 3.5.2 lvttl 5 volt tolerant inputs xclk_en symbol parameter min. typ. max. unit avdd18 dvdd18 xvdd18 lvdd18 supply voltage 1.71 1.8 1.89 v avdd33 dvdd33 supply voltage 3.135 3.3 3.465 v f xtal crystal frequency 27 mhz t oper ambient operating temperature 0 +70 c symbol parameter min. typ. max. unit r thja junction-to-ambient thermal resistance, 144-pin package 25 c/w r thja junction-to-ambient thermal resistance, 128-pin package 35 c/w symbol parameter condition min. typ. max. unit v ih high level input voltage 2.0 v v il low level input voltage 0.8 v v hyst schmitt trigger hysteresis 0.4 v symbol parameter condition min. typ. max. unit v ih high level input voltage 2.0 v v il low level input voltage 0.8 v
preliminary ac specifications ade3700 86/89 3.5.3 lvttl 5 volt tolerant i/o with hysteresis sda 3.5.4 lvttl outputs oba[0:7], oga[0:7], ora[0:7], obb[0:7], ogb[0:7], orb[0:7], ohs, ovs, ode, oclk 3.6 preliminary ac specifications symbol parameter condition min. typ. max. unit v ih high level input voltage 2.0 v v il low level input voltage 0.8 v v hyst schmitt trigger hysteresis 0.4 v symbol parameter condition min. typ. max. unit v ih high level input voltage 2.0 v v il low level input voltage 0.8 v i ih high level input current vin = vdd -10 a i il low level input current vin = 0v 10 a symbol parameter condition min. typ. max. unit vrsds_diff rsds differential output voltage rsds mode 100 200 400 mv vrsrs_cm rsds common mode output voltage 680 ohm + 50 ohm external termination to 1.3v 1.1 1.3 1.5 v trise, tfall rsds transition time to 90% cl = 30pf 3 ns inl adc integral nonlinearity (9-bit) 1.5 lsb dnl adc differential nonlinearity (9-bit) no missing codes 1.5 lsb vadc_in adc input voltage range 0.5 1 vp-p enob adc effective number of bits 135 msps input = 65 mhz sine at 95% fs 7.5 bits radc_in adc input resistance 200 kohms cadc_in adc input capacitance 8pf fadc adc sample frequency 20 140 mhz adc gain step adc gain step size 0.05 db adc offset step adc offset step size 4mv cadc_ext adc external ac coupling cap 0.1 uf
87/89 ade3700 preliminary ac specifications 4 package mechanical data dimensions (mm) dimensions (inches) min. typ. max. min. typ. max. a 1.600 0.063 a1 0.150 0.006 a2 1.400 1.350 1.450 0.055 0.053 0.057 b 0.220 0.170 0.270 0.009 0.007 0.011 d 22.000 0.866 d1 20.000 0.787 d2 e 16.000 0.623 e1 14.000 0.551 e2 e 0.500 0.020 l 0.600 0.450 0.750 0.024 0.0178 0.030 l1 1.000 0.040 k 0.000 7.000 0.000 0.275 d2 e2 d d1 b e pin 1 identification 11/13 e1 e a2 a1 gauge plane 0.25 mm. k 0 min. 0.08/0.20 r. 0.08 r. min. l l1 a
preliminary ac specifications ade3700 88/89 5 revision history table 38: summary of modifications date version description 12 august 2002 0.1 first draft 23 august 2002 0.2 addition of diagram on cover. modification of description and product selector info on 1st page. modification of section 2.7.1: functional description (smux) and table 11: sync multiplexer registers . modification of table 7: line lock pll registers , table 14: data measurement registers , table 15: lcd scaler registers and table 24: flicker registers . 17 october 2002 0.3 device named changed from ade3700x to ade3700. modification of block diagram and table on cover. 26 nov 2002 0.4 modification of registers smeas_v_ctrl and glbl_inclk_gate_ctrl 4 dec 2002 0.5 modification of package data (128-pin lqfp). 9 jan 2003 0.6 changes to pin description information. update of timing controller information. 10 july 2003 0.7 inclusion of section 3.2: power consumption matrices on page 84 .
89/89 ade3700 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. www.st.com

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